From: Chuck Ebbert <cebbert@redhat.com>
To: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
Cc: linux-kernel@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>
Subject: Re: x86_64 and AMD with C1E
Date: Wed, 24 Oct 2007 17:41:29 -0400 [thread overview]
Message-ID: <471FBC09.8050201@redhat.com> (raw)
In-Reply-To: <b70f2f960710241426y40d25647v3f25b275fad5ce76@mail.gmail.com>
On 10/24/2007 05:26 PM, Mikhail Kshevetskiy wrote:
>>>
>>> I fill something wrong here.
>>> Is it possible to reduce the amount of timer interrupts?
>>> Is it possible to force enable C1,C2 and C3 states when c1e disabled?
>>>
>> How are you disabling C1E?
>>
>>
> dirty hack, i just follow the FreeBSD way and clear C1e bit in lapic
> initialization code. I make it for test purpose only, so i do not produce a
> patch.
>
Why does disabling C1E disable C1, C2 and C3?
Thomas, in the case of the machines where C1E is disabled on CPU 0 but
enabled on CPU 1, could we just disable it? Maybe it's a BIOS bug and the
vendor just forgot to disable CPU 1...
next prev parent reply other threads:[~2007-10-24 21:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-10-01 6:15 x86_64 and AMD with C1E Mikhail Kshevetskiy
2007-10-01 9:33 ` Andi Kleen
[not found] ` <b70f2f960710010546k4658aa1ay466f243ac707c989@mail.gmail.com>
2007-10-01 12:50 ` Fwd: " Mikhail Kshevetskiy
2007-10-01 14:14 ` Thomas Gleixner
2007-10-01 14:32 ` Andi Kleen
2007-10-01 14:59 ` Thomas Gleixner
2007-10-01 15:21 ` Andi Kleen
2007-10-01 16:44 ` Thomas Gleixner
2007-10-01 17:56 ` Chuck Ebbert
2007-10-01 14:33 ` Mikhail Kshevetskiy
2007-10-01 13:09 ` Andi Kleen
2007-10-01 14:06 ` Arjan van de Ven
2007-10-01 14:40 ` Mikhail Kshevetskiy
2007-10-19 16:39 ` Chuck Ebbert
2007-10-24 21:26 ` Mikhail Kshevetskiy
2007-10-24 21:41 ` Chuck Ebbert [this message]
2007-10-24 22:12 ` Thomas Gleixner
2007-10-24 22:42 ` Mikhail Kshevetskiy
2007-12-15 11:06 ` Thomas Gleixner
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