* Re: [PATCH 2.6.24-rc5] x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai
2007-12-21 0:50 [PATCH 2.6.24-rc5] x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai Jason Gaston
@ 2007-12-21 0:31 ` Ingo Molnar
0 siblings, 0 replies; 2+ messages in thread
From: Ingo Molnar @ 2007-12-21 0:31 UTC (permalink / raw)
To: Jason Gaston; +Cc: linux-kernel, mingo
* Jason Gaston <jason.d.gaston@intel.com> wrote:
> This patch adds a cpu cache info entry for the Intel Tolapai cpu.
thanks, applied.
Ingo
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH 2.6.24-rc5] x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai
@ 2007-12-21 0:50 Jason Gaston
2007-12-21 0:31 ` Ingo Molnar
0 siblings, 1 reply; 2+ messages in thread
From: Jason Gaston @ 2007-12-21 0:50 UTC (permalink / raw)
To: jason.d.gaston, linux-kernel, mingo
This patch adds a cpu cache info entry for the Intel Tolapai cpu.
Signed-off-by: Jason Gaston <jason.d.gaston@intel.com>
--- linux-2.6.24-rc5/arch/x86/kernel/cpu/intel_cacheinfo.c.orig 2007-12-20 16:33:33.000000000 -0800
+++ linux-2.6.24-rc5/arch/x86/kernel/cpu/intel_cacheinfo.c 2007-12-20 16:34:22.000000000 -0800
@@ -49,6 +49,7 @@
{ 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
{ 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
{ 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
+ { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
{ 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
{ 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
{ 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
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2007-12-21 0:50 [PATCH 2.6.24-rc5] x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai Jason Gaston
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