From: Scott Wood <scottwood@freescale.com>
To: Poonam_Aggrwal-b10812 <b10812@freescale.com>
Cc: michael.barkowski@freescale.com, netdev@vger.kernel.org,
kumar.gala@freescale.com, linux-kernel@vger.kernel.org,
rubini@vision.unipv.it, linuxppc-dev@ozlabs.org,
ashish.kalra@freescale.com, rich.cutler@freescale.com,
akpm@linux-foundation.org, timur@freescale.com
Subject: Re: [PATCH UCC TDM 3/3 ] Modified Documentation to explain dts entries for TDM driver
Date: Thu, 24 Jan 2008 14:12:26 -0600 [thread overview]
Message-ID: <20080124201226.GA3926@loki.buserror.net> (raw)
In-Reply-To: <Pine.LNX.4.64.0801241022070.27491@linux121>
On Thu, Jan 24, 2008 at 10:24:13AM +0530, Poonam_Aggrwal-b10812 wrote:
> + ix) Baud Rate Generator (BRG)
> +
> + Required properties:
> + - compatible : shpuld be "fsl,cpm-brg"
> + - fsl,brg-sources : define the input clock for all 16 BRGs. The input
> + clock source could be 1 to 24 for CLK1 to CLK24. Zero means that the
> + particular BRG will be driven by QE clock(BRGCLK).
Should also have a clock-frequency property to specify what BRGCLK is.
-Scott
WARNING: multiple messages have this Message-ID (diff)
From: Scott Wood <scottwood@freescale.com>
To: Poonam_Aggrwal-b10812 <b10812@freescale.com>
Cc: kumar.gala@freescale.com, akpm@linux-foundation.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
rubini@vision.unipv.it, linuxppc-dev@ozlabs.org,
michael.barkowski@freescale.com, rich.cutler@freescale.com,
timur@freescale.com, ashish.kalra@freescale.com
Subject: Re: [PATCH UCC TDM 3/3 ] Modified Documentation to explain dts entries for TDM driver
Date: Thu, 24 Jan 2008 14:12:26 -0600 [thread overview]
Message-ID: <20080124201226.GA3926@loki.buserror.net> (raw)
In-Reply-To: <Pine.LNX.4.64.0801241022070.27491@linux121>
On Thu, Jan 24, 2008 at 10:24:13AM +0530, Poonam_Aggrwal-b10812 wrote:
> + ix) Baud Rate Generator (BRG)
> +
> + Required properties:
> + - compatible : shpuld be "fsl,cpm-brg"
> + - fsl,brg-sources : define the input clock for all 16 BRGs. The input
> + clock source could be 1 to 24 for CLK1 to CLK24. Zero means that the
> + particular BRG will be driven by QE clock(BRGCLK).
Should also have a clock-frequency property to specify what BRGCLK is.
-Scott
next prev parent reply other threads:[~2008-01-24 20:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-24 4:54 [PATCH UCC TDM 3/3 ] Modified Documentation to explain dts entries for TDM driver Poonam_Aggrwal-b10812
2008-01-24 4:54 ` Poonam_Aggrwal-b10812
2008-01-24 20:12 ` Scott Wood [this message]
2008-01-24 20:12 ` Scott Wood
2008-01-25 3:58 ` [PATCH UCC TDM 3/3 ] Modified Documentation to explain dtsentries " Aggrwal Poonam
2008-01-25 3:58 ` Aggrwal Poonam
2008-01-25 3:58 ` Aggrwal Poonam
2008-01-25 18:13 ` Scott Wood
2008-01-25 18:13 ` Scott Wood
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