Re: ndfc ecc byte order

[Stefan Roese <sr@denx.de>]

On Wednesday 30 January 2008, Stefan Roese wrote:
> On Wednesday 30 January 2008, Sean MacLennan wrote:
> > There seems to be a byte order conflict between the u-boot and Linux
> > ndfc drivers.
> >
> > u-boot has the following:
> >
> >     /* The NDFC uses Smart Media (SMC) bytes order*/
> >     ecc_code[0] = p[2];
> >     ecc_code[1] = p[1];
> >     ecc_code[2] = p[3];
> >
> > the kernel has:
> >
> >     ecc_code[0] = p[1];
> >     ecc_code[1] = p[2];
> >     ecc_code[2] = p[3];
> >
> > I think u-boot has it right since u-boot and kernel software calculated
> > ECCs agree. Anybody know a reason *not* to switch to the SMC byte order?
>
> Please take a look at Kconfig
>
> config MTD_NAND_NDFC
> 	tristate "NDFC NanD Flash Controller"
> 	depends on 4xx && !PPC_MERGE
> 	select MTD_NAND_ECC_SMC
>
> So the SMC byte ordering is selected and it should match the version used
> in U-Boot. In Linux the swapping is done in nand_ecc.c.

Seems that I was incorrect here. Tests showed that writing from Linux and then 
reading back from U-Boot results in ECC errors. My comment above is bogus, 
since nand_calculate_ecc() from nand_ecc.c is not used with HW-ECC generation 
enabled.

I'll send a patch to fix this in a short while.

Best regards,
Stefan