pending mips build fixes

pending mips build fixes

[Adrian Bunk]

Hi Ralf,

I hope I'm not too annoying on this, but I like it when as many 
defconfigs as possible compile.

Please review and push the following patches for 2.6.26:

  BCM47xx: Add platform specific PCI code
  http://marc.info/?l=linux-kernel&m=120876451216558&w=2

  MIPS: Fix CONF_CM_DEFAULT build error
  http://lkml.org/lkml/2008/6/1/125


That would get 3 more defconfigs compiling in 2.6.26.

TIA
Adrian

-- 

       "Is there not promise of rain?" Ling Tan asked suddenly out
        of the darkness. There had been need of rain for many days.
       "Only a promise," Lao Er said.
                                       Pearl S. Buck - Dragon Seed

Re: pending mips build fixes

[Ralf Baechle]

On Thu, Jun 12, 2008 at 04:45:40PM +0300, Adrian Bunk wrote:
> From: Adrian Bunk <bunk@kernel.org>
> Date: Thu, 12 Jun 2008 16:45:40 +0300
> To: ralf@linux-mips.org
> Cc: linux-mips@linux-mips.org, Michael Buesch <mb@bu3sch.de>,
> 	Aurelien Jarno <aurelien@aurel32.net>,
> 	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> Subject: pending mips build fixes
> Content-Type: text/plain; charset=utf-8
> 
> Hi Ralf,
> 
> I hope I'm not too annoying on this, but I like it when as many 
> defconfigs as possible compile.
> 
> Please review and push the following patches for 2.6.26:
> 
>   BCM47xx: Add platform specific PCI code
>   http://marc.info/?l=linux-kernel&amp;m=120876451216558&amp;w=2
> 
>   MIPS: Fix CONF_CM_DEFAULT build error
>   http://lkml.org/lkml/2008/6/1/125

That won't fly.  CONF_CM_DEFAULT is being dereferenced before
_page_cachable_default has been initialized.

Can't comment at the BCM47xx patch yet.

  Ralf

Re: pending mips build fixes

[Michael Buesch]

On Thursday 12 June 2008 15:58:35 Ralf Baechle wrote:
> On Thu, Jun 12, 2008 at 04:45:40PM +0300, Adrian Bunk wrote:
> > From: Adrian Bunk <bunk@kernel.org>
> > Date: Thu, 12 Jun 2008 16:45:40 +0300
> > To: ralf@linux-mips.org
> > Cc: linux-mips@linux-mips.org, Michael Buesch <mb@bu3sch.de>,
> > 	Aurelien Jarno <aurelien@aurel32.net>,
> > 	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> > Subject: pending mips build fixes
> > Content-Type: text/plain; charset=utf-8
> > 
> > Hi Ralf,
> > 
> > I hope I'm not too annoying on this, but I like it when as many 
> > defconfigs as possible compile.
> > 
> > Please review and push the following patches for 2.6.26:
> > 
> >   BCM47xx: Add platform specific PCI code
> >   http://marc.info/?l=linux-kernel&amp;m=120876451216558&amp;w=2

> Can't comment at the BCM47xx patch yet.

The 47xx patch is OK. It was a merge error by me. I simply forgot
to push these two functions upstream.

-- 
Greetings Michael.

Re: pending mips build fixes

[Atsushi Nemoto]

On Thu, 12 Jun 2008 14:58:35 +0100, Ralf Baechle <ralf@linux-mips.org> wrote:
> >   MIPS: Fix CONF_CM_DEFAULT build error
> >   http://lkml.org/lkml/2008/6/1/125
> 
> That won't fly.  CONF_CM_DEFAULT is being dereferenced before
> _page_cachable_default has been initialized.

Yes, And here is an updated untested patch.  Daniel, could you review
or try this?

------------------------------------------------------
Subject: MIPS: Fix pnx8550 build breakage
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>

This patch fix a breakage by commit
351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 > ([MIPS] Allow setting of
the cache attribute at run time.)

This patch introduce an weak __coherency_setup() to support PNX8550
which needs special handling on cache coherency updating.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/mm/c-r4k.c                       |   19 ++++++++++++-------
 arch/mips/nxp/pnx8550/jbs/board_setup.c    |   19 ++++++++++++-------
 arch/mips/nxp/pnx8550/stb810/board_setup.c |   19 ++++++++++++-------
 include/asm-mips/pgtable-bits.h            |    2 --
 4 files changed, 36 insertions(+), 23 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 643c8bc..d596b74 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1237,14 +1237,9 @@ static int __init cca_setup(char *str)
 
 __setup("cca=", cca_setup);
 
-static void __cpuinit coherency_setup(void)
+void __cpuinit __weak __coherency_setup(int ccaval)
 {
-	if (cca < 0 || cca > 7)
-		cca = read_c0_config() & CONF_CM_CMASK;
-	_page_cachable_default = cca << _CACHE_SHIFT;
-
-	pr_debug("Using cache attribute %d\n", cca);
-	change_c0_config(CONF_CM_CMASK, cca);
+	change_c0_config(CONF_CM_CMASK, ccaval);
 
 	/*
 	 * c0_status.cu=0 specifies that updates by the sc instruction use
@@ -1274,6 +1269,16 @@ static void __cpuinit coherency_setup(void)
 	}
 }
 
+static void __cpuinit coherency_setup(void)
+{
+	if (cca < 0 || cca > 7)
+		cca = read_c0_config() & CONF_CM_CMASK;
+	_page_cachable_default = cca << _CACHE_SHIFT;
+
+	pr_debug("Using cache attribute %d\n", cca);
+	__coherency_setup(cca);
+}
+
 #if defined(CONFIG_DMA_NONCOHERENT)
 
 static int __cpuinitdata coherentio;
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c
index f92826e..d528395 100644
--- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
+++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c
@@ -45,18 +45,23 @@
 				     "nop; nop; nop; nop; nop; nop;\n\t" \
 				     ".set reorder\n\t")
 
-void __init board_setup(void)
+void __cpuinit __coherency_setup(int ccaval)
 {
-	unsigned long config0, configpr;
-
-	config0 = read_c0_config();
+	unsigned long config0 = read_c0_config();
 
 	/* clear all three cache coherency fields */
-	config0 &= ~(0x7 | (7<<25) | (7<<28));
-	config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
-			(CONF_CM_DEFAULT<<28));
+	config0 &= ~(CONF_CM_CMASK | (CONF_CM_CMASK << 25) |
+			(CONF_CM_CMASK << 28));
+	config0 |= (ccaval | (ccaval << 25) | (ccaval << 28));
 	write_c0_config(config0);
 	BARRIER;
+}
+
+void __init board_setup(void)
+{
+	unsigned long configpr;
+
+	__coherency_setup(_CACHE_CACHABLE_NONCOHERENT >> _CACHE_SHIFT);
 
 	configpr = read_c0_config7();
 	configpr |= (1<<19); /* enable tlb */
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c
index 1282c27..7bd060f 100644
--- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
+++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c
@@ -31,17 +31,22 @@
 
 #include <glb.h>
 
-void __init board_setup(void)
+void __cpuinit __coherency_setup(int ccaval)
 {
-	unsigned long config0, configpr;
-
-	config0 = read_c0_config();
+	unsigned long config0 = read_c0_config();
 
 	/* clear all three cache coherency fields */
-	config0 &= ~(0x7 | (7<<25) | (7<<28));
-	config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
-			(CONF_CM_DEFAULT<<28));
+	config0 &= ~(CONF_CM_CMASK | (CONF_CM_CMASK << 25) |
+			(CONF_CM_CMASK << 28));
+	config0 |= (ccaval | (ccaval << 25) | (ccaval << 28));
 	write_c0_config(config0);
+}
+
+void __init board_setup(void)
+{
+	unsigned long configpr;
+
+	__coherency_setup(_CACHE_CACHABLE_NONCOHERENT >> _CACHE_SHIFT);
 
 	configpr = read_c0_config7();
 	configpr |= (1<<19); /* enable tlb */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 60e2f93..51b34a4 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -134,6 +134,4 @@
 
 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
 
-#define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
-
 #endif /* _ASM_PGTABLE_BITS_H */

Re: pending mips build fixes

[Ralf Baechle]

On Fri, Jun 13, 2008 at 12:03:50AM +0900, Atsushi Nemoto wrote:

> This patch fix a breakage by commit
> 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 > ([MIPS] Allow setting of
> the cache attribute at run time.)
> 
> This patch introduce an weak __coherency_setup() to support PNX8550
> which needs special handling on cache coherency updating.
> 
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>

Never been a fan of weak functions though depending circumstances they
certainly can be less evil than some of the alternatives.  Also what is
hidden deep in the PNX board code really is specific to the PNX CPU core,
so I moved it to c-r4k.c.  The resulting patch is below.

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 643c8bc..c41ea22 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1226,6 +1226,28 @@ void au1x00_fixup_config_od(void)
 	}
 }
 
+/* CP0 hazard avoidance. */
+#define NXP_BARRIER()							\
+	 __asm__ __volatile__(						\
+	".set noreorder\n\t"						\
+	"nop; nop; nop; nop; nop; nop;\n\t"				\
+	".set reorder\n\t")
+
+static void nxp_pr4450_fixup_config(void)
+{
+	unsigned long config0;
+
+	config0 = read_c0_config();
+
+	/* clear all three cache coherency fields */
+	config0 &= ~(0x7 | (7 << 25) | (7 << 28));
+	config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
+		    ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
+		    ((_page_cachable_default >> _CACHE_SHIFT) << 28));
+	write_c0_config(config0);
+	NXP_BARRIER();
+}
+
 static int __cpuinitdata cca = -1;
 
 static int __init cca_setup(char *str)
@@ -1271,6 +1293,10 @@ static void __cpuinit coherency_setup(void)
 	case CPU_AU1500: /* rev. AB */
 		au1x00_fixup_config_od();
 		break;
+
+	case PRID_IMP_PR4450:
+		nxp_pr4450_fixup_config();
+		break;
 	}
 }
 
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c
index f92826e..57dd903 100644
--- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
+++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c
@@ -47,16 +47,7 @@
 
 void __init board_setup(void)
 {
-	unsigned long config0, configpr;
-
-	config0 = read_c0_config();
-
-	/* clear all three cache coherency fields */
-	config0 &= ~(0x7 | (7<<25) | (7<<28));
-	config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
-			(CONF_CM_DEFAULT<<28));
-	write_c0_config(config0);
-	BARRIER;
+	unsigned long configpr;
 
 	configpr = read_c0_config7();
 	configpr |= (1<<19); /* enable tlb */
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c
index 1282c27..af2a55e 100644
--- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
+++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c
@@ -33,15 +33,7 @@
 
 void __init board_setup(void)
 {
-	unsigned long config0, configpr;
-
-	config0 = read_c0_config();
-
-	/* clear all three cache coherency fields */
-	config0 &= ~(0x7 | (7<<25) | (7<<28));
-	config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
-			(CONF_CM_DEFAULT<<28));
-	write_c0_config(config0);
+	unsigned long configpr;
 
 	configpr = read_c0_config7();
 	configpr |= (1<<19); /* enable tlb */

Re: pending mips build fixes

[danieljlaird]

Agree with the changes made

There is a larger problem however which is that I believe the 2.6.24 and 
later kernels broke PNX8550 support.
I tried to solve the issues (see some postings some time ago) regarding 
timer issues and changes made between 2.6.22 (working) and 2.6.24 broken.
However I could never get the fixes to work properly.  I have also since 
moved onto pastures new with the PNX833x/893x CPUs which means solving 
issues for a older CPU is not top of the list. And the lifetime of 8550 
willbe much shorter than the newer chipsets.

I would be tempted to mark PNX8550 / STB810 support as BROKEN.  Unless other 
8550 users can prove me wrong.
I would not remove the code yet incase it can be rescued but would mark as 
BROKEN in 2.6.27 and remove in 2.6.28
Cheers
Dan

--------------------------------------------------
From: "Ralf Baechle" <ralf@linux-mips.org>
Sent: Thursday, June 12, 2008 5:23 PM
To: "Atsushi Nemoto" <anemo@mba.ocn.ne.jp>
Cc: <bunk@kernel.org>; <linux-mips@linux-mips.org>; <mb@bu3sch.de>; 
<aurelien@aurel32.net>; <daniel.j.laird@nxp.com>
Subject: Re: pending mips build fixes

> On Fri, Jun 13, 2008 at 12:03:50AM +0900, Atsushi Nemoto wrote:
>
>> This patch fix a breakage by commit
>> 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 > ([MIPS] Allow setting of
>> the cache attribute at run time.)
>>
>> This patch introduce an weak __coherency_setup() to support PNX8550
>> which needs special handling on cache coherency updating.
>>
>> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>
> Never been a fan of weak functions though depending circumstances they
> certainly can be less evil than some of the alternatives.  Also what is
> hidden deep in the PNX board code really is specific to the PNX CPU core,
> so I moved it to c-r4k.c.  The resulting patch is below.
>
>  Ralf
>
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 643c8bc..c41ea22 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1226,6 +1226,28 @@ void au1x00_fixup_config_od(void)
>  }
> }
>
> +/* CP0 hazard avoidance. */
> +#define NXP_BARRIER() \
> + __asm__ __volatile__( \
> + ".set noreorder\n\t" \
> + "nop; nop; nop; nop; nop; nop;\n\t" \
> + ".set reorder\n\t")
> +
> +static void nxp_pr4450_fixup_config(void)
> +{
> + unsigned long config0;
> +
> + config0 = read_c0_config();
> +
> + /* clear all three cache coherency fields */
> + config0 &= ~(0x7 | (7 << 25) | (7 << 28));
> + config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
> +     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
> +     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
> + write_c0_config(config0);
> + NXP_BARRIER();
> +}
> +
> static int __cpuinitdata cca = -1;
>
> static int __init cca_setup(char *str)
> @@ -1271,6 +1293,10 @@ static void __cpuinit coherency_setup(void)
>  case CPU_AU1500: /* rev. AB */
>  au1x00_fixup_config_od();
>  break;
> +
> + case PRID_IMP_PR4450:
> + nxp_pr4450_fixup_config();
> + break;
>  }
> }
>
> diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c 
> b/arch/mips/nxp/pnx8550/jbs/board_setup.c
> index f92826e..57dd903 100644
> --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
> +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c
> @@ -47,16 +47,7 @@
>
> void __init board_setup(void)
> {
> - unsigned long config0, configpr;
> -
> - config0 = read_c0_config();
> -
> - /* clear all three cache coherency fields */
> - config0 &= ~(0x7 | (7<<25) | (7<<28));
> - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
> - (CONF_CM_DEFAULT<<28));
> - write_c0_config(config0);
> - BARRIER;
> + unsigned long configpr;
>
>  configpr = read_c0_config7();
>  configpr |= (1<<19); /* enable tlb */
> diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c 
> b/arch/mips/nxp/pnx8550/stb810/board_setup.c
> index 1282c27..af2a55e 100644
> --- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
> +++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c
> @@ -33,15 +33,7 @@
>
> void __init board_setup(void)
> {
> - unsigned long config0, configpr;
> -
> - config0 = read_c0_config();
> -
> - /* clear all three cache coherency fields */
> - config0 &= ~(0x7 | (7<<25) | (7<<28));
> - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
> - (CONF_CM_DEFAULT<<28));
> - write_c0_config(config0);
> + unsigned long configpr;
>
>  configpr = read_c0_config7();
>  configpr |= (1<<19); /* enable tlb */
>
> 

Re: pending mips build fixes

[danieljlaird]

Agree with the changes made

There is a larger problem however which is that I believe the 2.6.24 and 
later kernels broke PNX8550 support.
I tried to solve the issues (see some postings some time ago) regarding 
timer issues and changes made between 2.6.22 (working) and 2.6.24 broken.
However I could never get the fixes to work properly.  I have also since 
moved onto pastures new with the PNX833x/893x CPUs which means solving 
issues for a older CPU is not top of the list. And the lifetime of 8550 
willbe much shorter than the newer chipsets.

I would be tempted to mark PNX8550 / STB810 support as BROKEN.  Unless other 
8550 users can prove me wrong.
I would not remove the code yet incase it can be rescued but would mark as 
BROKEN in 2.6.27 and remove in 2.6.28
Cheers
Dan

--------------------------------------------------
From: "Ralf Baechle" <ralf@linux-mips.org>
Sent: Thursday, June 12, 2008 5:23 PM
To: "Atsushi Nemoto" <anemo@mba.ocn.ne.jp>
Cc: <bunk@kernel.org>; <linux-mips@linux-mips.org>; <mb@bu3sch.de>; 
<aurelien@aurel32.net>; <daniel.j.laird@nxp.com>
Subject: Re: pending mips build fixes

> On Fri, Jun 13, 2008 at 12:03:50AM +0900, Atsushi Nemoto wrote:
>
>> This patch fix a breakage by commit
>> 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 > ([MIPS] Allow setting of
>> the cache attribute at run time.)
>>
>> This patch introduce an weak __coherency_setup() to support PNX8550
>> which needs special handling on cache coherency updating.
>>
>> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>
> Never been a fan of weak functions though depending circumstances they
> certainly can be less evil than some of the alternatives.  Also what is
> hidden deep in the PNX board code really is specific to the PNX CPU core,
> so I moved it to c-r4k.c.  The resulting patch is below.
>
>  Ralf
>
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
>
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 643c8bc..c41ea22 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1226,6 +1226,28 @@ void au1x00_fixup_config_od(void)
>  }
> }
>
> +/* CP0 hazard avoidance. */
> +#define NXP_BARRIER() \
> + __asm__ __volatile__( \
> + ".set noreorder\n\t" \
> + "nop; nop; nop; nop; nop; nop;\n\t" \
> + ".set reorder\n\t")
> +
> +static void nxp_pr4450_fixup_config(void)
> +{
> + unsigned long config0;
> +
> + config0 = read_c0_config();
> +
> + /* clear all three cache coherency fields */
> + config0 &= ~(0x7 | (7 << 25) | (7 << 28));
> + config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
> +     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
> +     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
> + write_c0_config(config0);
> + NXP_BARRIER();
> +}
> +
> static int __cpuinitdata cca = -1;
>
> static int __init cca_setup(char *str)
> @@ -1271,6 +1293,10 @@ static void __cpuinit coherency_setup(void)
>  case CPU_AU1500: /* rev. AB */
>  au1x00_fixup_config_od();
>  break;
> +
> + case PRID_IMP_PR4450:
> + nxp_pr4450_fixup_config();
> + break;
>  }
> }
>
> diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c 
> b/arch/mips/nxp/pnx8550/jbs/board_setup.c
> index f92826e..57dd903 100644
> --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
> +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c
> @@ -47,16 +47,7 @@
>
> void __init board_setup(void)
> {
> - unsigned long config0, configpr;
> -
> - config0 = read_c0_config();
> -
> - /* clear all three cache coherency fields */
> - config0 &= ~(0x7 | (7<<25) | (7<<28));
> - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
> - (CONF_CM_DEFAULT<<28));
> - write_c0_config(config0);
> - BARRIER;
> + unsigned long configpr;
>
>  configpr = read_c0_config7();
>  configpr |= (1<<19); /* enable tlb */
> diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c 
> b/arch/mips/nxp/pnx8550/stb810/board_setup.c
> index 1282c27..af2a55e 100644
> --- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
> +++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c
> @@ -33,15 +33,7 @@
>
> void __init board_setup(void)
> {
> - unsigned long config0, configpr;
> -
> - config0 = read_c0_config();
> -
> - /* clear all three cache coherency fields */
> - config0 &= ~(0x7 | (7<<25) | (7<<28));
> - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
> - (CONF_CM_DEFAULT<<28));
> - write_c0_config(config0);
> + unsigned long configpr;
>
>  configpr = read_c0_config7();
>  configpr |= (1<<19); /* enable tlb */
>
> 

Re: pending mips build fixes

[Aurelien Jarno]

On Thu, Jun 12, 2008 at 04:31:57PM +0200, Michael Buesch wrote:
> On Thursday 12 June 2008 15:58:35 Ralf Baechle wrote:
> > On Thu, Jun 12, 2008 at 04:45:40PM +0300, Adrian Bunk wrote:
> > > From: Adrian Bunk <bunk@kernel.org>
> > > Date: Thu, 12 Jun 2008 16:45:40 +0300
> > > To: ralf@linux-mips.org
> > > Cc: linux-mips@linux-mips.org, Michael Buesch <mb@bu3sch.de>,
> > > 	Aurelien Jarno <aurelien@aurel32.net>,
> > > 	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> > > Subject: pending mips build fixes
> > > Content-Type: text/plain; charset=utf-8
> > > 
> > > Hi Ralf,
> > > 
> > > I hope I'm not too annoying on this, but I like it when as many 
> > > defconfigs as possible compile.
> > > 
> > > Please review and push the following patches for 2.6.26:
> > > 
> > >   BCM47xx: Add platform specific PCI code
> > >   http://marc.info/?l=linux-kernel&amp;m=120876451216558&amp;w=2
> 
> > Can't comment at the BCM47xx patch yet.
> 
> The 47xx patch is OK. It was a merge error by me. I simply forgot
> to push these two functions upstream.
> 

Any news on that?


-- 
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