From: "Aurélien Jarno" <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi to TCG
Date: Fri, 5 Sep 2008 16:18:47 +0200 [thread overview]
Message-ID: <20080905141847.GA22837@volta.aurel32.net> (raw)
In-Reply-To: <3970D476-0CFB-4F89-B06C-90FD9030AF8F@googlemail.com>
On Fri, Sep 05, 2008 at 12:53:56AM +0200, Andreas Färber wrote:
> Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.
>
> Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Applied thanks, but see my comment below.
> ---
> target-ppc/op.c | 13 -------------
> target-ppc/translate.c | 34 +++++++++++++++++++---------------
> 2 files changed, 19 insertions(+), 28 deletions(-)
>
> diff --git a/target-ppc/op.c b/target-ppc/op.c
> index 5451fd4..4ee411b 100644
> --- a/target-ppc/op.c
> +++ b/target-ppc/op.c
> @@ -602,12 +602,6 @@ void OPPROTO op_dec_ctr (void)
>
> /*** Integer arithmetic
> ***/
> /* add */
> -void OPPROTO op_add (void)
> -{
> - T0 += T1;
> - RETURN();
> -}
> -
> void OPPROTO op_check_addo (void)
> {
> xer_ov = (((uint32_t)T2 ^ (uint32_t)T1 ^ UINT32_MAX) &
> @@ -664,13 +658,6 @@ void OPPROTO op_adde_64 (void)
> }
> #endif
>
> -/* add immediate */
> -void OPPROTO op_addi (void)
> -{
> - T0 += (int32_t)PARAM1;
> - RETURN();
> -}
> -
> /* add to minus one extended */
> void OPPROTO op_add_me (void)
> {
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index d952276..f505be1 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 |
> 0x10, type)
> #endif
>
> /* add add. addo addo. */
> +static always_inline void gen_op_add (void)
> +{
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> +}
At some point, we will have to change this kind of function, otherwise
it will be really difficult to get rid of T0, T1 and T2.
> static always_inline void gen_op_addo (void)
> {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> gen_op_check_addo();
> }
> #if defined(TARGET_PPC64)
> @@ -838,7 +842,7 @@ static always_inline void gen_op_addo (void)
> static always_inline void gen_op_addo_64 (void)
> {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> gen_op_check_addo_64();
> }
> #endif
> @@ -847,13 +851,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08,
> PPC_INTEGER);
> static always_inline void gen_op_addc (void)
> {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> gen_op_check_addc();
> }
> static always_inline void gen_op_addco (void)
> {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> gen_op_check_addc();
> gen_op_check_addo();
> }
> @@ -861,13 +865,13 @@ static always_inline void gen_op_addco (void)
> static always_inline void gen_op_addc_64 (void)
> {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> gen_op_check_addc_64();
> }
> static always_inline void gen_op_addco_64 (void)
> {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> gen_op_check_addc_64();
> gen_op_check_addo_64();
> }
> @@ -1022,7 +1026,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> } else {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> - gen_op_addi(simm);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
> }
> tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
> }
> @@ -1034,7 +1038,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0)) {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_addi(simm);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode)
> gen_op_check_addc_64();
> @@ -1054,7 +1058,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF,
> 0x00000000, PPC_INTEGER)
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0)) {
> tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
> - gen_op_addi(simm);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
> #if defined(TARGET_PPC64)
> if (ctx->sf_mode)
> gen_op_check_addc_64();
> @@ -1078,7 +1082,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> } else {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> - gen_op_addi(simm << 16);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
> }
> tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
> }
> @@ -2118,7 +2122,7 @@ static always_inline void gen_addr_imm_index
> (DisasContext *ctx,
> } else {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> - gen_op_addi(simm);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
> }
> #ifdef DEBUG_MEMORY_ACCESSES
> gen_op_print_mem_EA();
> @@ -2132,7 +2136,7 @@ static always_inline void gen_addr_reg_index
> (DisasContext *ctx)
> } else {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> - gen_op_add();
> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
> }
> #ifdef DEBUG_MEMORY_ACCESSES
> gen_op_print_mem_EA();
> @@ -2331,7 +2335,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000,
> PPC_64BX)
> gen_addr_imm_index(ctx, 0x0F);
> op_ldst(ld);
> tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
> - gen_op_addi(8);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
> op_ldst(ld);
> tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]);
> #endif
> @@ -2427,7 +2431,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000,
> PPC_64B)
> gen_addr_imm_index(ctx, 0x03);
> tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
> op_ldst(std);
> - gen_op_addi(8);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8);
> tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
> op_ldst(std);
> #endif
> @@ -5346,7 +5350,7 @@ static always_inline void gen_addr_spe_imm_index
> (DisasContext *ctx, int sh)
> } else {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
> if (likely(simm != 0))
> - gen_op_addi(simm << sh);
> + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh);
> }
> }
>
> --
> 1.5.5.1
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
next prev parent reply other threads:[~2008-09-05 14:20 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-02 13:36 [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG Andreas Färber
2008-09-02 14:32 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Andreas Färber
2008-09-02 15:39 ` [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 " Andreas Färber
2008-09-02 16:19 ` Aurelien Jarno
2008-09-02 16:57 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Andreas Färber
2008-09-02 22:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} " Andreas Färber
2008-09-02 23:20 ` Aurelien Jarno
2008-09-03 0:39 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Andreas Färber
2008-09-03 5:07 ` Aurelien Jarno
2008-09-03 10:41 ` Andreas Färber
2008-09-03 11:28 ` Thiemo Seufer
2008-09-03 18:07 ` Andreas Färber
2008-09-03 18:26 ` Blue Swirl
2008-09-03 19:00 ` Andreas Färber
2008-09-03 19:12 ` Blue Swirl
2008-09-03 20:04 ` [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves " Andreas Färber
2008-09-04 5:25 ` Aurelien Jarno
2008-09-04 10:21 ` Andreas Färber
2008-09-04 12:24 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register " Andreas Färber
2008-09-04 14:08 ` [Qemu-devel] [PATCH 7/x] ppc: Convert FPR " Andreas Färber
2008-09-04 14:39 ` Aurélien Jarno
2008-09-04 17:59 ` [Qemu-devel] [PATCH 8/x] ppc: Convert op_set_FT0 " Andreas Färber
2008-09-04 20:36 ` Aurélien Jarno
2008-09-04 22:53 ` [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi " Andreas Färber
2008-09-05 14:18 ` Aurélien Jarno [this message]
2008-09-05 17:17 ` Andreas Färber
2008-09-05 17:49 ` Aurelien Jarno
2008-09-04 23:46 ` [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf " Andreas Färber
2008-09-05 14:18 ` Aurélien Jarno
2008-09-04 14:39 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register moves " Aurélien Jarno
2008-09-07 14:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Paul Brook
2008-09-03 12:41 ` Aurélien Jarno
2008-09-03 12:58 ` Andreas Färber
2008-09-03 13:00 ` Aurélien Jarno
2008-09-03 13:23 ` Thiemo Seufer
2008-09-03 13:45 ` Tristan Gingold
2008-09-03 16:04 ` Andreas Färber
2008-09-02 23:27 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Aurélien Jarno
2008-09-02 15:58 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Aurelien Jarno
2008-09-02 16:44 ` [Qemu-devel] [PATCH 2/x v2] " Andreas Färber
2008-09-02 23:28 ` Aurélien Jarno
2008-09-02 16:18 ` [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} " Aurelien Jarno
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