Re: [PATCH 0/6] MSI-INTx interrupt translation for HVM

[Qing He <qing.he@intel.com>]

On Thu, 2009-01-08 at 18:44 +0800, Shohei Fujiwara wrote:
> I have one question.
> 
> MSI interrupt is edge-triggered, and INTx interrupt is level-triggered.
> Guest OS handles translated interrupt as level-triggered, though physical
> interrupt is edge-triggered. When two interrupts are raised during short
> period, Guest OS might lose 2nd interrupt, I think.

This problem is handled by a different EOI timing. As soon as the
hypervisor receives an MSI, it issues the EOI ASAP, and the duration of
the injected level-triggered IRQ and guest EOI are all handled by the
virtual APICs. If a 2nd interrupt comes up at this time, the hypervisor
can receive the EOI and this results in a pending IRQ in virtual APICs
instead of lost.

Generally, it's easy to "translate" an edged interrupt to a level one,
but not the other way.

Thanks,
Qing
> 
> What do you think?
> 
> Thanks,
> --
> Shohei Fujiwara
>