From: Ralf Baechle <ralf@linux-mips.org>
To: VomLehn <dvomlehn@cisco.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>, linux-mips@linux-mips.org
Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay
Date: Tue, 10 Mar 2009 21:12:25 +0100 [thread overview]
Message-ID: <20090310201224.GA12379@linux-mips.org> (raw)
In-Reply-To: <20090310191828.GA30449@cuplxvomd02.corp.sa.net>
On Tue, Mar 10, 2009 at 12:18:28PM -0700, VomLehn wrote:
> > > +config CP0_COUNT_NDELAY
> > > + bool "Use coprocessor 0 Count register for ndelay functionality"
> > > + default n
> >
> > Does there need to be some sort of depends here to cover off any
> > limitations where it is known that it won't work?
>
> I don't have the breadth of knowledge required to say what processors have
> a CP0 Count register. Any suggestions?
All MIPS III, MIPS IV, MIPS32 and MIPS64 processors have a 32-bit count
register which typically is clocked at half the maximum instruction issue
rate, more rarely at the full rate. A few processors like the RM53230
family can select the increment rate at reset-time to either the full or
half instruction issue rate. Others have the option of totally halting
it in special low-power, low-performance modes. The count rate might also
be affected by clock scaling.
Ralf
next prev parent reply other threads:[~2009-03-10 20:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-02-27 23:09 [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay VomLehn
2009-02-28 21:10 ` Paul Gortmaker
2009-02-28 21:10 ` Paul Gortmaker
2009-03-10 19:18 ` VomLehn
2009-03-10 20:12 ` Ralf Baechle [this message]
-- strict thread matches above, loose matches on Subject: below --
2009-03-12 3:28 VomLehn
2009-03-13 9:29 ` Thomas Bogendoerfer
2009-03-13 11:32 ` Ralf Baechle
2009-03-13 17:35 ` VomLehn
[not found] <web-5716826@test.infohit.si>
2009-03-25 17:37 ` David VomLehn
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