From: David VomLehn <dvomlehn@cisco.com>
To: Mauricio Culibrk <mauricio@infohit.si>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay
Date: Wed, 25 Mar 2009 10:37:49 -0700 [thread overview]
Message-ID: <49CA6BED.60505@cisco.com> (raw)
In-Reply-To: <web-5716826@test.infohit.si>
Mauricio Culibrk wrote:
> Hi there!
>
> I'm really sorry for bothering you.... I noticed your posts and patch on
> the linux-mips mailing list....
> and I'm very interested in ndelay patch you proposed.
>
> I'm currently using some embedded mips-based boards for bit-banging SPI
> and I2C implementations... but the current code uses udelay which is way
> too "long" for the purporse...
>
> I'm wondering if you have any updated/fixed patch available as you
> mention that on the list (that you'll fix your patch a little regarding
> all the comments received)
>
> Anyway... I'm using some "consumer" boards based on Atheros WiSoCs
> AR2315, AR2317... and Broadcom chips which should have MIPS32 MIPS4K
> cores...
> this cpu should have a "functioning cr0 register", right? (as I have
> absolutely no "datasheets" available to check for that)
The latest version of the ndelay patch is version 3, which disables
interrupts to ensure the Count register doesn't wrap. If you have
interrupts disabled already, there is another function you can can call.
You can get the version 3 patch from the mailing list archive at
http://www.linux-mips.org/archives/linux-mips/2009-03/msg00073.html
I haven't received much feedback since the first version of the patch,
and it's something we're already using, so I think it's in pretty good
shape. And, as I understand it, R4000-series processors should be in
shape as far as a good Count register. Part of the version 3 patch adds
dependencies so that it will only appear in your favorite configuration
tool if you've selected a processor on which it will work. Ralf has
mentioned some issues with some R4000 processors, though.
As the code stands on my 24K processor, a requested delay of 100 nsec
ends up as an actual delay of a bit over 130 nsec. Not perfect, but
definitely less than 1000 nsec. I have been thinking about adding in a
calibration constant that should get it closer, but it hasn't been
important yet and I wanted the basic patch to get accepted before I did
anything *really* obscure.
next parent reply other threads:[~2009-03-25 17:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <web-5716826@test.infohit.si>
2009-03-25 17:37 ` David VomLehn [this message]
2009-03-12 3:28 [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay VomLehn
2009-03-13 9:29 ` Thomas Bogendoerfer
2009-03-13 11:32 ` Ralf Baechle
2009-03-13 17:35 ` VomLehn
-- strict thread matches above, loose matches on Subject: below --
2009-02-27 23:09 VomLehn
2009-02-28 21:10 ` Paul Gortmaker
2009-02-28 21:10 ` Paul Gortmaker
2009-03-10 19:18 ` VomLehn
2009-03-10 20:12 ` Ralf Baechle
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=49CA6BED.60505@cisco.com \
--to=dvomlehn@cisco.com \
--cc=linux-mips@linux-mips.org \
--cc=mauricio@infohit.si \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.