From: David Brownell <david-b@pacbell.net>
To: "vimal singh" <vimalsingh@ti.com>
Cc: davinci-linux-open-source@linux.davincidsp.com,
nsnehaprabha@ti.com, linux-mtd@lists.infradead.org,
akpm@linux-foundation.org, dwmw2@infradead.org,
tglx@linutronix.de
Subject: Re: [PATCH 2/2] NAND on DM355: Add 4-bit ECC support for large page NAND chips
Date: Thu, 7 May 2009 02:11:05 -0700 [thread overview]
Message-ID: <200905070211.05491.david-b@pacbell.net> (raw)
In-Reply-To: <46149.192.168.10.89.1241686785.squirrel@dbdmail.itg.ti.com>
On Thursday 07 May 2009, vimal singh wrote:
> > Comments would be good, highlighting (a) byte 5 is reserved,
> > it's the manufacturer bad block marker, (b) 8 bytes @16 are
> > expected by JFFS2. Not everyone will "just know" those.
>
> How about leaving bytes '4' and '5' for bad block marker, to support 16-bit
> NAND parts too.
This 4-bit ECC engine only works for 8-bit wide parts ...
or are you suggesting that in case TI re-engineers that
engine in the future?
next prev parent reply other threads:[~2009-05-07 9:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-07 8:59 [PATCH 2/2] NAND on DM355: Add 4-bit ECC support for large page NAND chips vimal singh
2009-05-07 9:11 ` David Brownell [this message]
[not found] <43965.192.168.10.89.1241763647.squirrel@dbdmail.itg.ti.com>
2009-05-09 4:24 ` vimal singh
[not found] <46149.192.168.10.89.1241686786.squirrel@dbdmail.itg.ti.com>
2009-05-07 9:50 ` vimal singh
2009-05-07 16:54 ` David Brownell
-- strict thread matches above, loose matches on Subject: below --
2009-05-07 2:29 nsnehaprabha
2009-05-07 7:16 ` David Brownell
2009-05-07 14:13 ` Narnakaje, Snehaprabha
2009-05-07 17:11 ` David Brownell
2009-05-07 18:02 ` Narnakaje, Snehaprabha
2009-05-07 22:37 ` Troy Kisky
2009-05-08 0:03 ` Narnakaje, Snehaprabha
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