From: Grant Grundler <grundler@parisc-linux.org>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Tejun Heo <tj@kernel.org>,
linux-pci@vger.kernel.org, Greg KH <greg@kroah.com>,
Linux Kernel <linux-kernel@vger.kernel.org>,
towerlexa@gmx.de
Subject: Re: Who's responsible for configuring CLS on a cardbus device?
Date: Fri, 29 May 2009 10:53:31 -0600 [thread overview]
Message-ID: <20090529165331.GD28355@lackof.org> (raw)
In-Reply-To: <20090526142300.73d466d0@lxorguk.ukuu.org.uk>
On Tue, May 26, 2009 at 02:23:00PM +0100, Alan Cox wrote:
...
> > This is solvable by simply setting CLS to the correct value but who's
> > job is it? For non-hotplug devices, this is configured by the BIOS
> > (at least on PC), so for hotplug devices I think falls on the lap of
> > the PCI code but I'm not sure. If this is something which the
> > sata_sil driver should be responsible for, is there an established way
> > to determine the proper CLS value?
>
> Currently its handled by pci_set_mwi() but there isn't actually a more
> direct way to do this.
There isn't for the drivers because BIOS is supposed to set
PCI_CACHE_LINE_SIZE.
If the BIOS isn't setting PCI_CACHE_LINE_SIZE, the arch specific
pci support should be checking PCI_CACHE_LINE_SIZE and/or setting
it in pcibios_set_master().
hth,
grant
prev parent reply other threads:[~2009-05-29 16:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-26 13:05 Who's responsible for configuring CLS on a cardbus device? Tejun Heo
2009-05-26 13:23 ` Alan Cox
2009-05-26 23:44 ` Robert Hancock
2009-05-26 23:51 ` Tejun Heo
2009-05-27 0:19 ` Kenji Kaneshige
2009-05-27 13:32 ` [RFC PATCH] pccard: configure CLS on attach Tejun Heo
2009-05-27 14:03 ` Matthew Wilcox
2009-05-27 23:11 ` Tejun Heo
2009-05-28 6:46 ` Benjamin Herrenschmidt
2009-06-05 5:49 ` Axel Birndt
2009-05-29 16:53 ` Grant Grundler [this message]
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