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From: Tejun Heo <tj@kernel.org>
To: Robert Hancock <hancockrwd@gmail.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>,
	linux-pci@vger.kernel.org, Greg KH <greg@kroah.com>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	towerlexa@gmx.de
Subject: Re: Who's responsible for configuring CLS on a cardbus device?
Date: Wed, 27 May 2009 08:51:45 +0900	[thread overview]
Message-ID: <4A1C8091.4050909@kernel.org> (raw)
In-Reply-To: <4A1C7EF9.2030000@gmail.com>

Hello,

Robert Hancock wrote:
> Alan Cox wrote:
>> Currently its handled by pci_set_mwi() but there isn't actually a more
>> direct way to do this.

Thanks Alan.

> Yeah, I guess the assumption is that unless the device is using MWI it
> doesn't care about cache line size. However, in the case of the sata_sil
> controllers (and possibly other devices), the device cares about it for
> other purposes (I think it's FIFO handling in this case).
> 
> Maybe we should just be setting the cache line size somewhere more
> basic, like pci_set_master or something?

Hmmm... given that it is something which is usually handled by the
system firmware, wouldn't it be more fitting to configure it from pci
hotplug code?

Thanks.

-- 
tejun

  reply	other threads:[~2009-05-26 23:50 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-26 13:05 Who's responsible for configuring CLS on a cardbus device? Tejun Heo
2009-05-26 13:23 ` Alan Cox
2009-05-26 23:44   ` Robert Hancock
2009-05-26 23:51     ` Tejun Heo [this message]
2009-05-27  0:19       ` Kenji Kaneshige
2009-05-27 13:32         ` [RFC PATCH] pccard: configure CLS on attach Tejun Heo
2009-05-27 14:03           ` Matthew Wilcox
2009-05-27 23:11             ` Tejun Heo
2009-05-28  6:46               ` Benjamin Herrenschmidt
2009-06-05  5:49           ` Axel Birndt
2009-05-29 16:53   ` Who's responsible for configuring CLS on a cardbus device? Grant Grundler

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