* [PATCH 1/2 -tip] x86: perf_counter check AMD performance monitoring support @ 2009-06-11 9:58 Jaswinder Singh Rajput 2009-06-11 9:59 ` [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table Jaswinder Singh Rajput 2009-06-13 14:49 ` [tip:perfcounters/core] perf_counter, x86: Check old-AMD performance monitoring support tip-bot for Jaswinder Singh Rajput 0 siblings, 2 replies; 8+ messages in thread From: Jaswinder Singh Rajput @ 2009-06-11 9:58 UTC (permalink / raw) To: Ingo Molnar, Thomas Gleixner, x86 maintainers, LKML AMD supports performance monitoring from K7. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> --- arch/x86/kernel/cpu/perf_counter.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 57ae1be..719a7d5 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -1452,6 +1452,10 @@ static int intel_pmu_init(void) static int amd_pmu_init(void) { + /* performance-monitoring supported from K7 */ + if (boot_cpu_data.x86 < 6) + return -ENODEV; + x86_pmu = amd_pmu; switch (boot_cpu_data.x86) { -- 1.6.0.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table 2009-06-11 9:58 [PATCH 1/2 -tip] x86: perf_counter check AMD performance monitoring support Jaswinder Singh Rajput @ 2009-06-11 9:59 ` Jaswinder Singh Rajput 2009-06-12 17:35 ` Ingo Molnar 2009-06-13 14:49 ` [tip:perfcounters/core] perf_counter, x86: Check old-AMD performance monitoring support tip-bot for Jaswinder Singh Rajput 1 sibling, 1 reply; 8+ messages in thread From: Jaswinder Singh Rajput @ 2009-06-11 9:59 UTC (permalink / raw) To: Ingo Molnar; +Cc: Thomas Gleixner, x86 maintainers, LKML AMD shares same hw caching related event table. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> --- arch/x86/kernel/cpu/perf_counter.c | 36 +++++++++++++++--------------------- 1 files changed, 15 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 719a7d5..e7c9500 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -389,23 +389,23 @@ static u64 intel_pmu_raw_event(u64 event) return event & CORE_EVNTSEL_MASK; } -static const u64 amd_0f_hw_cache_event_ids +static const u64 amd_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { [ C(L1D) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ + [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ }, }, [ C(L1I ) ] = { @@ -418,17 +418,17 @@ static const u64 amd_0f_hw_cache_event_ids [ C(RESULT_MISS) ] = -1, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ [ C(RESULT_MISS) ] = 0, }, }, [ C(L2 ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ + [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { @@ -438,8 +438,8 @@ static const u64 amd_0f_hw_cache_event_ids }, [ C(DTLB) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -1458,16 +1458,10 @@ static int amd_pmu_init(void) x86_pmu = amd_pmu; - switch (boot_cpu_data.x86) { - case 0x0f: - case 0x10: - case 0x11: - memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids, - sizeof(hw_cache_event_ids)); + /* Events are common for all AMDs */ + memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); - pr_cont("AMD Family 0f/10/11 events, "); - break; - } return 0; } -- 1.6.0.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table 2009-06-11 9:59 ` [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table Jaswinder Singh Rajput @ 2009-06-12 17:35 ` Ingo Molnar 2009-06-12 19:35 ` Jaswinder Singh Rajput 0 siblings, 1 reply; 8+ messages in thread From: Ingo Molnar @ 2009-06-12 17:35 UTC (permalink / raw) To: Jaswinder Singh Rajput; +Cc: Thomas Gleixner, x86 maintainers, LKML * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote: > AMD shares same hw caching related event table. > > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> > --- > arch/x86/kernel/cpu/perf_counter.c | 36 +++++++++++++++--------------------- > 1 files changed, 15 insertions(+), 21 deletions(-) Looks good - but your patch does not apply anymore. (Neither to -git nor to -tip) Ingo ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table 2009-06-12 17:35 ` Ingo Molnar @ 2009-06-12 19:35 ` Jaswinder Singh Rajput 2009-06-12 19:36 ` Jaswinder Singh Rajput 0 siblings, 1 reply; 8+ messages in thread From: Jaswinder Singh Rajput @ 2009-06-12 19:35 UTC (permalink / raw) To: Ingo Molnar; +Cc: Thomas Gleixner, x86 maintainers, LKML On Fri, 2009-06-12 at 19:35 +0200, Ingo Molnar wrote: > * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote: > > > AMD shares same hw caching related event table. > > > > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> > > --- > > arch/x86/kernel/cpu/perf_counter.c | 36 +++++++++++++++--------------------- > > 1 files changed, 15 insertions(+), 21 deletions(-) > > Looks good - but your patch does not apply anymore. (Neither to -git > nor to -tip) > It is because of L2 -> LL Here are new patches : [PATCH 1/2 -tip] x86: perf_counter check AMD performance monitoring support AMD supports performance monitoring from K7. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> --- arch/x86/kernel/cpu/perf_counter.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 275bc14..b74e602 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -1459,6 +1459,10 @@ static int intel_pmu_init(void) static int amd_pmu_init(void) { + /* performance-monitoring supported from K7 */ + if (boot_cpu_data.x86 < 6) + return -ENODEV; + x86_pmu = amd_pmu; switch (boot_cpu_data.x86) { -- 1.6.0.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table 2009-06-12 19:35 ` Jaswinder Singh Rajput @ 2009-06-12 19:36 ` Jaswinder Singh Rajput 2009-06-13 11:03 ` Ingo Molnar 2009-06-13 14:49 ` [tip:perfcounters/core] perf_counter, x86: Update " tip-bot for Jaswinder Singh Rajput 0 siblings, 2 replies; 8+ messages in thread From: Jaswinder Singh Rajput @ 2009-06-12 19:36 UTC (permalink / raw) To: Ingo Molnar; +Cc: Thomas Gleixner, x86 maintainers, LKML On Sat, 2009-06-13 at 01:05 +0530, Jaswinder Singh Rajput wrote: > On Fri, 2009-06-12 at 19:35 +0200, Ingo Molnar wrote: > > * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote: > > > > > AMD shares same hw caching related event table. > > > > > > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> > > > --- > > > arch/x86/kernel/cpu/perf_counter.c | 36 +++++++++++++++--------------------- > > > 1 files changed, 15 insertions(+), 21 deletions(-) > > > > Looks good - but your patch does not apply anymore. (Neither to -git > > nor to -tip) > > > > It is because of L2 -> LL > > Here are new patches : > > [PATCH 1/2 -tip] x86: perf_counter check AMD performance monitoring support [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table AMD shares same hw caching related event table. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> --- arch/x86/kernel/cpu/perf_counter.c | 36 +++++++++++++++--------------------- 1 files changed, 15 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index b74e602..0e747e5 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -389,23 +389,23 @@ static u64 intel_pmu_raw_event(u64 event) return event & CORE_EVNTSEL_MASK; } -static const u64 amd_0f_hw_cache_event_ids +static const u64 amd_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { [ C(L1D) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ + [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ }, }, [ C(L1I ) ] = { @@ -418,17 +418,17 @@ static const u64 amd_0f_hw_cache_event_ids [ C(RESULT_MISS) ] = -1, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ [ C(RESULT_MISS) ] = 0, }, }, [ C(LL ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ + [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { @@ -438,8 +438,8 @@ static const u64 amd_0f_hw_cache_event_ids }, [ C(DTLB) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -1465,16 +1465,10 @@ static int amd_pmu_init(void) x86_pmu = amd_pmu; - switch (boot_cpu_data.x86) { - case 0x0f: - case 0x10: - case 0x11: - memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids, - sizeof(hw_cache_event_ids)); + /* Events are common for all AMDs */ + memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); - pr_cont("AMD Family 0f/10/11 events, "); - break; - } return 0; } -- 1.6.0.6 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table 2009-06-12 19:36 ` Jaswinder Singh Rajput @ 2009-06-13 11:03 ` Ingo Molnar 2009-06-13 14:49 ` [tip:perfcounters/core] perf_counter, x86: Update " tip-bot for Jaswinder Singh Rajput 1 sibling, 0 replies; 8+ messages in thread From: Ingo Molnar @ 2009-06-13 11:03 UTC (permalink / raw) To: Jaswinder Singh Rajput; +Cc: Thomas Gleixner, x86 maintainers, LKML * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote: > [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table > > AMD shares same hw caching related event table. > > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> > - [ C(RESULT_ACCESS) ] = 0, > - [ C(RESULT_MISS) ] = 0, > + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ > + [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ How did you get to these numbers and have you tested them? (Such information needs to be in the changelog) Ingo ^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip:perfcounters/core] perf_counter, x86: Update AMD hw caching related event table 2009-06-12 19:36 ` Jaswinder Singh Rajput 2009-06-13 11:03 ` Ingo Molnar @ 2009-06-13 14:49 ` tip-bot for Jaswinder Singh Rajput 1 sibling, 0 replies; 8+ messages in thread From: tip-bot for Jaswinder Singh Rajput @ 2009-06-13 14:49 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, acme, paulus, hpa, mingo, a.p.zijlstra, efault, jaswinder, jaswinderrajput, robert.richter, tglx, mingo Commit-ID: f4db43a38f7387c3b19c9565124c06ab0c5d6e9a Gitweb: http://git.kernel.org/tip/f4db43a38f7387c3b19c9565124c06ab0c5d6e9a Author: Jaswinder Singh Rajput <jaswinder@kernel.org> AuthorDate: Sat, 13 Jun 2009 01:06:21 +0530 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Sat, 13 Jun 2009 12:58:25 +0200 perf_counter, x86: Update AMD hw caching related event table All AMD models share the same hw caching related event table. Also complete the table with more events. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <1244835381.2802.2.camel@ht.satnam> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/cpu/perf_counter.c | 36 +++++++++++++++--------------------- 1 files changed, 15 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 3c37c39..77a59a5 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -389,23 +389,23 @@ static u64 intel_pmu_raw_event(u64 event) return event & CORE_EVNTSEL_MASK; } -static const u64 amd_0f_hw_cache_event_ids +static const u64 amd_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { [ C(L1D) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ + [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ }, }, [ C(L1I ) ] = { @@ -418,17 +418,17 @@ static const u64 amd_0f_hw_cache_event_ids [ C(RESULT_MISS) ] = -1, }, [ C(OP_PREFETCH) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ [ C(RESULT_MISS) ] = 0, }, }, [ C(LL ) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ + [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ }, [ C(OP_WRITE) ] = { - [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ [ C(RESULT_MISS) ] = 0, }, [ C(OP_PREFETCH) ] = { @@ -438,8 +438,8 @@ static const u64 amd_0f_hw_cache_event_ids }, [ C(DTLB) ] = { [ C(OP_READ) ] = { - [ C(RESULT_ACCESS) ] = 0, - [ C(RESULT_MISS) ] = 0, + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ + [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0, @@ -1465,16 +1465,10 @@ static int amd_pmu_init(void) x86_pmu = amd_pmu; - switch (boot_cpu_data.x86) { - case 0x0f: - case 0x10: - case 0x11: - memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids, - sizeof(hw_cache_event_ids)); + /* Events are common for all AMDs */ + memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); - pr_cont("AMD Family 0f/10/11 events, "); - break; - } return 0; } ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [tip:perfcounters/core] perf_counter, x86: Check old-AMD performance monitoring support 2009-06-11 9:58 [PATCH 1/2 -tip] x86: perf_counter check AMD performance monitoring support Jaswinder Singh Rajput 2009-06-11 9:59 ` [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table Jaswinder Singh Rajput @ 2009-06-13 14:49 ` tip-bot for Jaswinder Singh Rajput 1 sibling, 0 replies; 8+ messages in thread From: tip-bot for Jaswinder Singh Rajput @ 2009-06-13 14:49 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, acme, paulus, hpa, mingo, a.p.zijlstra, efault, jaswinder, jaswinderrajput, robert.richter, tglx, mingo Commit-ID: 4d2be1267fcfb3a4d2198fd696aec5e3dcbce60e Gitweb: http://git.kernel.org/tip/4d2be1267fcfb3a4d2198fd696aec5e3dcbce60e Author: Jaswinder Singh Rajput <jaswinder@kernel.org> AuthorDate: Thu, 11 Jun 2009 15:28:09 +0530 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Sat, 13 Jun 2009 12:58:25 +0200 perf_counter, x86: Check old-AMD performance monitoring support AMD supports performance monitoring start from K7 (i.e. family 6), so disable it for earlier AMD CPUs. Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <1244714289.6923.0.camel@ht.satnam> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/cpu/perf_counter.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 275bc14..3c37c39 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c @@ -1459,6 +1459,10 @@ static int intel_pmu_init(void) static int amd_pmu_init(void) { + /* Performance-monitoring supported from K7 and later: */ + if (boot_cpu_data.x86 < 6) + return -ENODEV; + x86_pmu = amd_pmu; switch (boot_cpu_data.x86) { ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2009-06-13 14:51 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-06-11 9:58 [PATCH 1/2 -tip] x86: perf_counter check AMD performance monitoring support Jaswinder Singh Rajput 2009-06-11 9:59 ` [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table Jaswinder Singh Rajput 2009-06-12 17:35 ` Ingo Molnar 2009-06-12 19:35 ` Jaswinder Singh Rajput 2009-06-12 19:36 ` Jaswinder Singh Rajput 2009-06-13 11:03 ` Ingo Molnar 2009-06-13 14:49 ` [tip:perfcounters/core] perf_counter, x86: Update " tip-bot for Jaswinder Singh Rajput 2009-06-13 14:49 ` [tip:perfcounters/core] perf_counter, x86: Check old-AMD performance monitoring support tip-bot for Jaswinder Singh Rajput
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