Re: [PATCH] [SVM]: Make 32bit legacy guests boot again

[Christoph Egger <Christoph.Egger@amd.com>]

Confirmed. Now both 32bit and 64bit guests boot.

Christoph


On Monday 29 June 2009 16:51:19 Keir Fraser wrote:
> I'm flying blind since I don't have an AMD box to hand to test on, but I
> think changeset 19869 will probably fix this.
>
>  -- Keir
>
> On 29/06/2009 12:36, "Christoph Egger" <Christoph.Egger@amd.com> wrote:
> > Your changes broke the boot of 64bit guests. I see a triple fault now.
> >
> > Christoph
> >
> > On Monday 29 June 2009 11:17:39 Keir Fraser wrote:
> >> I forgot to push. Should be there now.
> >>
> >>   -- Keir
> >>
> >> On 29/06/2009 09:39, "Christoph Egger" <Christoph.Egger@amd.com> wrote:
> >>> Tnx. I will check as soon as it appears in the public staging tree.
> >>>
> >>> Christoph
> >>>
> >>> On Saturday 27 June 2009 11:35:20 Keir Fraser wrote:
> >>>> Changeset 19856 is a cleaned up and streamlined version of this patch.
> >>>> Please take a look. It also fixes a couple of largely theoretical
> >>>> issues: * Should depend on EFER.LMA not EFER.LME
> >>>>  * Should handle the LMA 1->0 transition (i.e., return to legacy
> >>>> mode).
> >>>>
> >>>>  -- Keir
> >>>>
> >>>> On 26/06/2009 16:19, "Christoph Egger" <Christoph.Egger@amd.com> wrote:
> >>>>> Hi!
> >>>>>
> >>>>> Attached patch fixes a bug introduced in c/s 19648.
> >>>>>
> >>>>> 32bit legacy guests have the sysenter/sysexit instructions available.
> >>>>> Therefore, we have to disable intercepts for the sysenter MSRs or the
> >>>>> guest stucks in an infinite loop of #GPs, otherwise.
> >>>>>
> >>>>> For guests in 64bit mode and 32bit compat mode, sysenter/sysexit
> >>>>> instructions aren't available. The sysenter MSRs have to be
> >>>>> intercepted to make the instruction emulation working.
> >>>>>
> >>>>> Attach patch first assumes the guest is in 32bit legacy mode and
> >>>>> therefore disables the sysenter MSRs in construct_vmcb().
> >>>>> Access to the MSR_EFER is intercepted. When the guest enables
> >>>>> longmode, then enable interception of the sysenter MSRs.
> >>>>>
> >>>>> Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>



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