From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney@caviumnetworks.com>
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2).
Date: Wed, 1 Jul 2009 19:20:51 +0100 [thread overview]
Message-ID: <20090701182051.GB23121@linux-mips.org> (raw)
In-Reply-To: <4A4AB845.1030906@caviumnetworks.com>
On Tue, Jun 30, 2009 at 06:13:41PM -0700, David Daney wrote:
> The problem with CPU_MIPS64_R2 in the kernel is that it means two
> unrelated things:
>
> 1) The cpu can execute all mips64r2 ISA instructions.
>
> 2) The cpu requires that all worse case cache and execution hazards are
> handled.
>
> In the case of the Octeon processors, #1 is true, but we can get better
> performance by omitting many of the hazard barriers because they are
> unneeded.
The most performance sensitive hazard barriers are the ones in the TLB
exception handlers and they're now being handled in C code in tlbex.c
which mostly does runtime decissions. I suspect the remaining hazard
barriers are not a big performance thing anymore.
Ralf
prev parent reply other threads:[~2009-07-01 18:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-29 16:54 [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2) David Daney
2009-06-29 19:34 ` Ralf Baechle
2009-07-01 0:37 ` Maciej W. Rozycki
2009-07-01 1:13 ` David Daney
2009-07-01 1:36 ` Maciej W. Rozycki
2009-07-01 18:40 ` Ralf Baechle
2009-07-01 18:20 ` Ralf Baechle [this message]
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