From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: David Daney <ddaney@caviumnetworks.com>, linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2).
Date: Wed, 1 Jul 2009 19:40:27 +0100 [thread overview]
Message-ID: <20090701184027.GC23121@linux-mips.org> (raw)
In-Reply-To: <alpine.LFD.2.00.0907010234320.23134@eddie.linux-mips.org>
On Wed, Jul 01, 2009 at 02:36:31AM +0100, Maciej W. Rozycki wrote:
> > The problem with CPU_MIPS64_R2 in the kernel is that it means two unrelated
> > things:
> >
> > 1) The cpu can execute all mips64r2 ISA instructions.
> >
> > 2) The cpu requires that all worse case cache and execution hazards are
> > handled.
> >
> > In the case of the Octeon processors, #1 is true, but we can get better
> > performance by omitting many of the hazard barriers because they are unneeded.
>
> Which is why I think a split of the semantics would be a good idea.
That's the idea since a long time. There are far less uses of CONFIG_CPU_*
than there used to be historically - and usually they're a bug or at least
should be considered one.
Ralf
next prev parent reply other threads:[~2009-07-01 18:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-29 16:54 [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2) David Daney
2009-06-29 19:34 ` Ralf Baechle
2009-07-01 0:37 ` Maciej W. Rozycki
2009-07-01 1:13 ` David Daney
2009-07-01 1:36 ` Maciej W. Rozycki
2009-07-01 18:40 ` Ralf Baechle [this message]
2009-07-01 18:20 ` Ralf Baechle
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