[PATCH v2 1/4] S3C: sdhci: Fix incorrect clock option for SDHCI base clock.

[PATCH v2 1/4] S3C: sdhci: Fix incorrect clock option for SDHCI base clock.

[Thomas Abraham]

The third base clock option for SDHCI controller in S3C64XX is
mout_epll. This patch removes mmc_bus clock and uses mout_epll
as the third clock option for SDHCI base clock.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
 arch/arm/mach-s3c6410/setup-sdhci.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
index 20666f3..aaac505 100644
--- a/arch/arm/mach-s3c6410/setup-sdhci.c
+++ b/arch/arm/mach-s3c6410/setup-sdhci.c
@@ -29,7 +29,7 @@
 char *s3c6410_hsmmc_clksrcs[4] = {
 	[0] = "hsmmc",
 	[1] = "hsmmc",
-	[2] = "mmc_bus",
+	[2] = "mout_epll",
 	/* [3] = "48m", - note not succesfully used yet */
 };
 
-- 
1.5.3.4

Re: [PATCH v2 1/4] S3C: sdhci: Fix incorrect clock option for SDHCI base clock.

[Ben Dooks]

On Thu, Oct 15, 2009 at 02:48:18PM +0900, Thomas Abraham wrote:
> The third base clock option for SDHCI controller in S3C64XX is
> mout_epll. This patch removes mmc_bus clock and uses mout_epll
> as the third clock option for SDHCI base clock.

I thought the MMC bus clock was the one that was gated through the
SCLK_MMC0 and the CLKSRC_MMC0 divider system which takes not only the
mout_epll, but dout_epll, fin_epll and the 27m clock, as so:

static struct clk *clkset_spi_mmc_list[] = {
        &clk_mout_epll.clk,
        &clk_dout_mpll,
        &clk_fin_epll,
        &clk_27m,
};

So I don't think this change is the right one but I don't have any
docummentation to hand as I'm currently attending ELC09.

> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
>  arch/arm/mach-s3c6410/setup-sdhci.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c6410/setup-sdh2Aci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
> index 20666f3..aaac505 100644
> --- a/arch/arm/mach-s3c6410/setup-sdhci.c
> +++ b/arch/arm/mach-s3c6410/setup-sdhci.c
> @@ -29,7 +29,7 @@
>  char *s3c6410_hsmmc_clksrcs[4] = {
>  	[0] = "hsmmc",
>  	[1] = "hsmmc",
> -	[2] = "mmc_bus",
> +	[2] = "mout_epll",
>  	/* [3] = "48m", - note not succesfully used yet */
>  };
>  
> -- 
> 1.5.3.4
> 
> --
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-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

Re: [PATCH v2 1/4] S3C: sdhci: Fix incorrect clock option for SDHCI base clock.

[Thomas Abraham]

Hi Ben,

On Fri, Oct 16, 2009 at 6:44 AM, Ben Dooks <ben-linux@fluff.org> wrote:
> On Thu, Oct 15, 2009 at 02:48:18PM +0900, Thomas Abraham wrote:
>> The third base clock option for SDHCI controller in S3C64XX is
>> mout_epll. This patch removes mmc_bus clock and uses mout_epll
>> as the third clock option for SDHCI base clock.
>
> I thought the MMC bus clock was the one that was gated through the
> SCLK_MMC0 and the CLKSRC_MMC0 divider system which takes not only the
> mout_epll, but dout_epll, fin_epll and the 27m clock, as so:
>
> static struct clk *clkset_spi_mmc_list[] = {
>        &clk_mout_epll.clk,
>        &clk_dout_mpll,
>        &clk_fin_epll,
>        &clk_27m,
> };
>
> So I don't think this change is the right one but I don't have any
> docummentation to hand as I'm currently attending ELC09.
>

As per the 6410 user manual, the 6410 SDHCI controller module receives
two clocks - CLKMMCx and SDHCI controller base clock.

The CLKMMCx clock source can be derived from one of the four possible
parent clocks - mout_epll, dout_mpll, fin_epll and 27Mhz. The parent
clock is selected using the MMC mux and it goes through a divider
before being used as CLKMMCx.

The SDHCI controller base clock can be derived from one the four
possible parent clocks - hclk, hclk, epll and ext clock. The parent
clock for base clock is selected using CONTROL2[5:4] register bits.
The CONTROL2 register is part of the SDHCI controller module.

The CLKMMCx clock is represented using the name "mmc_bus" in
"plat-s3c64xx/s3c6400-clock.c" file.

The list of parent clock sources for second clock (SDHCI base clock)
is listed in "mach-s3c6410/setup-sdhci.c" file
(s3c6410_hsmmc_clksrcs). In this list, "mmc_bus" was listed as parent
clock. This, I feel is not correct because "mmc_bus" clock is the
CLKMMCx clock. So this patch replaced "mmc_bus" with "mout_epll" as
the clock source (which is as per the spec).

Please let us know your opinion.

Thanks,
Thomas.