* [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate clean lines
@ 2009-12-09 18:43 ` Santosh Shilimkar
0 siblings, 0 replies; 16+ messages in thread
From: Santosh Shilimkar @ 2009-12-09 18:43 UTC (permalink / raw)
To: linux-arm-kernel
This patch implements the work-around for the errata 588369. The secure API
is used to alter L2 debug regsiter because of trust-zone.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/Kconfig | 13 +++++++++++++
arch/arm/mm/cache-l2x0.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf8a99f..388d1e3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -916,6 +916,19 @@ config ARM_ERRATA_460075
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
+config PL310_ERRATA_588369
+ bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+ depends on CACHE_L2X0
+ default n
+ help
+ The PL310 L2 cache controller implements three types of Clean &
+ Invalidate maintenance operations: by Physical Address
+ (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+ They are architecturally defined to behave as the execution of a
+ clean operation followed immediately by an invalidate operation,
+ both performing to the same memory location. This functionality
+ is not correctly implemented in PL310 as clean lines are not
+ invalidated as a result of these operations
endmenu
source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 747f9a9..c3905a9 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -88,8 +88,40 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
unsigned long addr;
start &= ~(CACHE_LINE_SIZE - 1);
+#ifdef CONFIG_PL310_ERRATA_588369
+ /*
+ * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
+ * Control Register)
+ */
+ __asm__ __volatile__(
+ "stmfd r13!, {r0-r12, r14}\n"
+ "mov r0, #3\n"
+ "ldr r12, =0x100\n"
+ "dsb\n"
+ "smc\n"
+ "ldmfd r13!, {r0-r12, r14}");
+
+ /* Clean by PA followed by Invalidate by PA */
+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE) {
+ sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
+ sync_writel(addr, L2X0_INV_LINE_PA, 1);
+ }
+
+ /*
+ * Enable Write-Back and Cache Linefill (set bits [1:0] of the Debug
+ * Control Register)
+ */
+ __asm__ __volatile__(
+ "stmfd r13!, {r0-r12, r14}\n"
+ "mov r0, #0\n"
+ "ldr r12, =0x100\n"
+ "dsb\n"
+ "smc\n"
+ "ldmfd r13!, {r0-r12, r14}");
+#else
for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
+#endif
cache_sync();
}
--
1.6.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/4] OMAP4: Enable L2 Cache
2009-12-09 18:43 ` Santosh Shilimkar
@ 2009-12-09 18:43 ` Santosh Shilimkar
-1 siblings, 0 replies; 16+ messages in thread
From: Santosh Shilimkar @ 2009-12-09 18:43 UTC (permalink / raw)
To: tony; +Cc: linux-arm-kernel, linux-omap, linux, Santosh Shilimkar
This patch enables L2 cache and associated Errata on the OMAP4430
SDP.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/configs/omap_4430sdp_defconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 49df3ad..2a8d555 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -243,10 +243,13 @@ CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
CONFIG_ARM_L1_CACHE_SHIFT=5
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_PL310_ERRATA_588369=y
CONFIG_ARM_GIC=y
#
--
1.6.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/4] OMAP4: Enable L2 Cache
@ 2009-12-09 18:43 ` Santosh Shilimkar
0 siblings, 0 replies; 16+ messages in thread
From: Santosh Shilimkar @ 2009-12-09 18:43 UTC (permalink / raw)
To: linux-arm-kernel
This patch enables L2 cache and associated Errata on the OMAP4430
SDP.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
arch/arm/configs/omap_4430sdp_defconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 49df3ad..2a8d555 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -243,10 +243,13 @@ CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
CONFIG_ARM_L1_CACHE_SHIFT=5
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_PL310_ERRATA_588369=y
CONFIG_ARM_GIC=y
#
--
1.6.0.4
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate clean lines
2009-12-09 18:43 ` Santosh Shilimkar
@ 2009-12-09 19:19 ` Tony Lindgren
-1 siblings, 0 replies; 16+ messages in thread
From: Tony Lindgren @ 2009-12-09 19:19 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-arm-kernel, linux-omap
Hi,
* Santosh Shilimkar <santosh.shilimkar@ti.com> [091209 10:42]:
> This patch implements the work-around for the errata 588369. The secure API
> is used to alter L2 debug regsiter because of trust-zone.
This one should be queued via Russell's patch system. It should
be also acked by Catalin.
Regards,
Tony
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/Kconfig | 13 +++++++++++++
> arch/arm/mm/cache-l2x0.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index cf8a99f..388d1e3 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -916,6 +916,19 @@ config ARM_ERRATA_460075
> ACTLR register. Note that setting specific bits in the ACTLR register
> may not be available in non-secure mode.
>
> +config PL310_ERRATA_588369
> + bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
> + depends on CACHE_L2X0
> + default n
> + help
> + The PL310 L2 cache controller implements three types of Clean &
> + Invalidate maintenance operations: by Physical Address
> + (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
> + They are architecturally defined to behave as the execution of a
> + clean operation followed immediately by an invalidate operation,
> + both performing to the same memory location. This functionality
> + is not correctly implemented in PL310 as clean lines are not
> + invalidated as a result of these operations
> endmenu
>
> source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 747f9a9..c3905a9 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -88,8 +88,40 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
> unsigned long addr;
>
> start &= ~(CACHE_LINE_SIZE - 1);
> +#ifdef CONFIG_PL310_ERRATA_588369
> + /*
> + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> + * Control Register)
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #3\n"
> + "ldr r12, =0x100\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
> +
> + /* Clean by PA followed by Invalidate by PA */
> + for (addr = start; addr < end; addr += CACHE_LINE_SIZE) {
> + sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
> + sync_writel(addr, L2X0_INV_LINE_PA, 1);
> + }
> +
> + /*
> + * Enable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> + * Control Register)
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #0\n"
> + "ldr r12, =0x100\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
> +#else
> for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
> sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
> +#endif
> cache_sync();
> }
>
> --
> 1.6.0.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate clean lines
@ 2009-12-09 19:19 ` Tony Lindgren
0 siblings, 0 replies; 16+ messages in thread
From: Tony Lindgren @ 2009-12-09 19:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
* Santosh Shilimkar <santosh.shilimkar@ti.com> [091209 10:42]:
> This patch implements the work-around for the errata 588369. The secure API
> is used to alter L2 debug regsiter because of trust-zone.
This one should be queued via Russell's patch system. It should
be also acked by Catalin.
Regards,
Tony
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/Kconfig | 13 +++++++++++++
> arch/arm/mm/cache-l2x0.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index cf8a99f..388d1e3 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -916,6 +916,19 @@ config ARM_ERRATA_460075
> ACTLR register. Note that setting specific bits in the ACTLR register
> may not be available in non-secure mode.
>
> +config PL310_ERRATA_588369
> + bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
> + depends on CACHE_L2X0
> + default n
> + help
> + The PL310 L2 cache controller implements three types of Clean &
> + Invalidate maintenance operations: by Physical Address
> + (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
> + They are architecturally defined to behave as the execution of a
> + clean operation followed immediately by an invalidate operation,
> + both performing to the same memory location. This functionality
> + is not correctly implemented in PL310 as clean lines are not
> + invalidated as a result of these operations
> endmenu
>
> source "arch/arm/common/Kconfig"
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 747f9a9..c3905a9 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -88,8 +88,40 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
> unsigned long addr;
>
> start &= ~(CACHE_LINE_SIZE - 1);
> +#ifdef CONFIG_PL310_ERRATA_588369
> + /*
> + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> + * Control Register)
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #3\n"
> + "ldr r12, =0x100\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
> +
> + /* Clean by PA followed by Invalidate by PA */
> + for (addr = start; addr < end; addr += CACHE_LINE_SIZE) {
> + sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
> + sync_writel(addr, L2X0_INV_LINE_PA, 1);
> + }
> +
> + /*
> + * Enable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> + * Control Register)
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #0\n"
> + "ldr r12, =0x100\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
> +#else
> for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
> sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
> +#endif
> cache_sync();
> }
>
> --
> 1.6.0.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do notinvalidate clean lines
2009-12-09 18:43 ` Santosh Shilimkar
@ 2009-12-14 10:37 ` Catalin Marinas
-1 siblings, 0 replies; 16+ messages in thread
From: Catalin Marinas @ 2009-12-14 10:37 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: tony, linux-omap, linux, linux-arm-kernel
On Wed, 2009-12-09 at 18:43 +0000, Santosh Shilimkar wrote:
> This patch implements the work-around for the errata 588369. The secure API
> is used to alter L2 debug regsiter because of trust-zone.
[...]
> +config PL310_ERRATA_588369
> + bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
> + depends on CACHE_L2X0
> + default n
> + help
> + The PL310 L2 cache controller implements three types of Clean &
> + Invalidate maintenance operations: by Physical Address
> + (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
> + They are architecturally defined to behave as the execution of a
> + clean operation followed immediately by an invalidate operation,
> + both performing to the same memory location. This functionality
> + is not correctly implemented in PL310 as clean lines are not
> + invalidated as a result of these operations
> endmenu
Could you actually add a comment and a dependence on OMAP4 since this
requires the secure monitor that only TI has.
>
> +#ifdef CONFIG_PL310_ERRATA_588369
> + /*
> + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> + * Control Register)
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #3\n"
> + "ldr r12, =0x100\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
Could you actually add a function that gets called with a parameter
rather than having to similar inline asm blocks? You also don't need to
save/restore the registers if you declare them properly or use local
variables for that, the compiler does the work for you.
Is a DSB needed before SMC (I'm not sure)?
--
Catalin
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do notinvalidate clean lines
@ 2009-12-14 10:37 ` Catalin Marinas
0 siblings, 0 replies; 16+ messages in thread
From: Catalin Marinas @ 2009-12-14 10:37 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2009-12-09 at 18:43 +0000, Santosh Shilimkar wrote:
> This patch implements the work-around for the errata 588369. The secure API
> is used to alter L2 debug regsiter because of trust-zone.
[...]
> +config PL310_ERRATA_588369
> + bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
> + depends on CACHE_L2X0
> + default n
> + help
> + The PL310 L2 cache controller implements three types of Clean &
> + Invalidate maintenance operations: by Physical Address
> + (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
> + They are architecturally defined to behave as the execution of a
> + clean operation followed immediately by an invalidate operation,
> + both performing to the same memory location. This functionality
> + is not correctly implemented in PL310 as clean lines are not
> + invalidated as a result of these operations
> endmenu
Could you actually add a comment and a dependence on OMAP4 since this
requires the secure monitor that only TI has.
>
> +#ifdef CONFIG_PL310_ERRATA_588369
> + /*
> + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> + * Control Register)
> + */
> + __asm__ __volatile__(
> + "stmfd r13!, {r0-r12, r14}\n"
> + "mov r0, #3\n"
> + "ldr r12, =0x100\n"
> + "dsb\n"
> + "smc\n"
> + "ldmfd r13!, {r0-r12, r14}");
Could you actually add a function that gets called with a parameter
rather than having to similar inline asm blocks? You also don't need to
save/restore the registers if you declare them properly or use local
variables for that, the compiler does the work for you.
Is a DSB needed before SMC (I'm not sure)?
--
Catalin
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do notinvalidate clean lines
2009-12-14 10:37 ` Catalin Marinas
@ 2009-12-14 10:52 ` Shilimkar, Santosh
-1 siblings, 0 replies; 16+ messages in thread
From: Shilimkar, Santosh @ 2009-12-14 10:52 UTC (permalink / raw)
To: Catalin Marinas
Cc: tony@atomide.com, linux-omap@vger.kernel.org,
linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org
Thanks for comments Catalin !!
> -----Original Message-----
> From: Catalin Marinas [mailto:catalin.marinas@arm.com]
> Sent: Monday, December 14, 2009 4:07 PM
> To: Shilimkar, Santosh
> Cc: tony@atomide.com; linux-omap@vger.kernel.org; linux@arm.linux.org.uk; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do notinvalidate clean lines
>
> On Wed, 2009-12-09 at 18:43 +0000, Santosh Shilimkar wrote:
> > This patch implements the work-around for the errata 588369. The secure API
> > is used to alter L2 debug regsiter because of trust-zone.
> [...]
> > +config PL310_ERRATA_588369
> > + bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
> > + depends on CACHE_L2X0
> > + default n
> > + help
> > + The PL310 L2 cache controller implements three types of Clean &
> > + Invalidate maintenance operations: by Physical Address
> > + (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
> > + They are architecturally defined to behave as the execution of a
> > + clean operation followed immediately by an invalidate operation,
> > + both performing to the same memory location. This functionality
> > + is not correctly implemented in PL310 as clean lines are not
> > + invalidated as a result of these operations
> > endmenu
>
> Could you actually add a comment and a dependence on OMAP4 since this
> requires the secure monitor that only TI has.
OK
> > +#ifdef CONFIG_PL310_ERRATA_588369
> > + /*
> > + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> > + * Control Register)
> > + */
> > + __asm__ __volatile__(
> > + "stmfd r13!, {r0-r12, r14}\n"
> > + "mov r0, #3\n"
> > + "ldr r12, =0x100\n"
> > + "dsb\n"
> > + "smc\n"
> > + "ldmfd r13!, {r0-r12, r14}");
>
> Could you actually add a function that gets called with a parameter
> rather than having to similar inline asm blocks? You also don't need to
> save/restore the registers if you declare them properly or use local
> variables for that, the compiler does the work for you.
A function call would be better as you suggested. We will look into this.
> Is a DSB needed before SMC (I'm not sure)?
That was a recommendation though not having it, I didn't observer any problems.
> --
> Catalin
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do notinvalidate clean lines
@ 2009-12-14 10:52 ` Shilimkar, Santosh
0 siblings, 0 replies; 16+ messages in thread
From: Shilimkar, Santosh @ 2009-12-14 10:52 UTC (permalink / raw)
To: linux-arm-kernel
Thanks for comments Catalin !!
> -----Original Message-----
> From: Catalin Marinas [mailto:catalin.marinas at arm.com]
> Sent: Monday, December 14, 2009 4:07 PM
> To: Shilimkar, Santosh
> Cc: tony at atomide.com; linux-omap at vger.kernel.org; linux at arm.linux.org.uk; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate do notinvalidate clean lines
>
> On Wed, 2009-12-09 at 18:43 +0000, Santosh Shilimkar wrote:
> > This patch implements the work-around for the errata 588369. The secure API
> > is used to alter L2 debug regsiter because of trust-zone.
> [...]
> > +config PL310_ERRATA_588369
> > + bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
> > + depends on CACHE_L2X0
> > + default n
> > + help
> > + The PL310 L2 cache controller implements three types of Clean &
> > + Invalidate maintenance operations: by Physical Address
> > + (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
> > + They are architecturally defined to behave as the execution of a
> > + clean operation followed immediately by an invalidate operation,
> > + both performing to the same memory location. This functionality
> > + is not correctly implemented in PL310 as clean lines are not
> > + invalidated as a result of these operations
> > endmenu
>
> Could you actually add a comment and a dependence on OMAP4 since this
> requires the secure monitor that only TI has.
OK
> > +#ifdef CONFIG_PL310_ERRATA_588369
> > + /*
> > + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> > + * Control Register)
> > + */
> > + __asm__ __volatile__(
> > + "stmfd r13!, {r0-r12, r14}\n"
> > + "mov r0, #3\n"
> > + "ldr r12, =0x100\n"
> > + "dsb\n"
> > + "smc\n"
> > + "ldmfd r13!, {r0-r12, r14}");
>
> Could you actually add a function that gets called with a parameter
> rather than having to similar inline asm blocks? You also don't need to
> save/restore the registers if you declare them properly or use local
> variables for that, the compiler does the work for you.
A function call would be better as you suggested. We will look into this.
> Is a DSB needed before SMC (I'm not sure)?
That was a recommendation though not having it, I didn't observer any problems.
> --
> Catalin
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate donotinvalidate clean lines
2009-12-14 10:52 ` Shilimkar, Santosh
@ 2009-12-14 11:09 ` Catalin Marinas
-1 siblings, 0 replies; 16+ messages in thread
From: Catalin Marinas @ 2009-12-14 11:09 UTC (permalink / raw)
To: Shilimkar, Santosh; +Cc: tony, linux-omap, linux, linux-arm-kernel
On Mon, 2009-12-14 at 10:52 +0000, Shilimkar, Santosh wrote:
> > On Wed, 2009-12-09 at 18:43 +0000, Santosh Shilimkar wrote:
> > > +#ifdef CONFIG_PL310_ERRATA_588369
> > > + /*
> > > + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> > > + * Control Register)
> > > + */
> > > + __asm__ __volatile__(
> > > + "stmfd r13!, {r0-r12, r14}\n"
> > > + "mov r0, #3\n"
> > > + "ldr r12, =0x100\n"
> > > + "dsb\n"
> > > + "smc\n"
> > > + "ldmfd r13!, {r0-r12, r14}");
[...]
> > Is a DSB needed before SMC (I'm not sure)?
>
> That was a recommendation though not having it, I didn't observer any problems.
Maybe it's needed, I'm not sure, but if you found it recommended in some
errata description, then you probably need it.
--
Catalin
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 3/4] ARM: L2 : Errata 588369: Clean & Invalidate donotinvalidate clean lines
@ 2009-12-14 11:09 ` Catalin Marinas
0 siblings, 0 replies; 16+ messages in thread
From: Catalin Marinas @ 2009-12-14 11:09 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 2009-12-14 at 10:52 +0000, Shilimkar, Santosh wrote:
> > On Wed, 2009-12-09 at 18:43 +0000, Santosh Shilimkar wrote:
> > > +#ifdef CONFIG_PL310_ERRATA_588369
> > > + /*
> > > + * Disable Write-Back and Cache Linefill (set bits [1:0] of the Debug
> > > + * Control Register)
> > > + */
> > > + __asm__ __volatile__(
> > > + "stmfd r13!, {r0-r12, r14}\n"
> > > + "mov r0, #3\n"
> > > + "ldr r12, =0x100\n"
> > > + "dsb\n"
> > > + "smc\n"
> > > + "ldmfd r13!, {r0-r12, r14}");
[...]
> > Is a DSB needed before SMC (I'm not sure)?
>
> That was a recommendation though not having it, I didn't observer any problems.
Maybe it's needed, I'm not sure, but if you found it recommended in some
errata description, then you probably need it.
--
Catalin
^ permalink raw reply [flat|nested] 16+ messages in thread