S5PC100 common code cleanups

S5PC100 common code cleanups

[Ben Dooks]

A couple of pathces to move the S5PC100 to use common plat-samsung code.

[PATCH] ARM: S5PC1XX: Move to using standard timer IRQ handling code

[Ben Dooks]

From: Ben Dooks <ben-linux@fluff.org>

Move to using the standard VIC/Timer IRQ handling code added previously\
to avoid duplicating code.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
 arch/arm/mach-s5pc100/include/mach/tick.h |    2 +-
 arch/arm/plat-s5pc1xx/Kconfig             |    2 +
 arch/arm/plat-s5pc1xx/include/plat/irqs.h |   19 ++++--
 arch/arm/plat-s5pc1xx/irq.c               |   88 ++--------------------------
 4 files changed, 23 insertions(+), 88 deletions(-)

diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index d3de0f3..f338c9e 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -21,7 +21,7 @@
 static inline u32 s3c24xx_ostimer_pending(void)
 {
 	u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
-	return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0));
+	return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0));
 }
 
 #define TICK_MAX	(0xffffffff)
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 5d97b1c..6438bcd 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -12,11 +12,13 @@ config PLAT_S5PC1XX
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select SAMSUNG_CLKSRC
+	select SAMSUNG_IRQ_VIC_TIMER
 	select S3C_GPIO_TRACK
 	select S3C_GPIO_PULL_UPDOWN
 	select S3C_GPIO_CFG_S3C24XX
 	select S3C_GPIO_CFG_S3C64XX
 	select S5P_GPIO_CFG_S5PC1XX
+	select SAMSUNG_IRQ_VIC_TIMER
 	help
 	  Base platform code for any Samsung S5PC1XX device
 
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
index ef87363..409c804 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -88,11 +88,11 @@
 #define IRQ_MDMA		S5PC1XX_IRQ_VIC0(18)
 #define IRQ_PDMA0		S5PC1XX_IRQ_VIC0(19)
 #define IRQ_PDMA1		S5PC1XX_IRQ_VIC0(20)
-#define IRQ_TIMER0		S5PC1XX_IRQ_VIC0(21)
-#define IRQ_TIMER1		S5PC1XX_IRQ_VIC0(22)
-#define IRQ_TIMER2		S5PC1XX_IRQ_VIC0(23)
-#define IRQ_TIMER3		S5PC1XX_IRQ_VIC0(24)
-#define IRQ_TIMER4		S5PC1XX_IRQ_VIC0(25)
+#define IRQ_TIMER0_VIC		S5PC1XX_IRQ_VIC0(21)
+#define IRQ_TIMER1_VIC		S5PC1XX_IRQ_VIC0(22)
+#define IRQ_TIMER2_VIC		S5PC1XX_IRQ_VIC0(23)
+#define IRQ_TIMER3_VIC		S5PC1XX_IRQ_VIC0(24)
+#define IRQ_TIMER4_VIC		S5PC1XX_IRQ_VIC0(25)
 #define IRQ_SYSTIMER		S5PC1XX_IRQ_VIC0(26)
 #define IRQ_WDT			S5PC1XX_IRQ_VIC0(27)
 #define IRQ_RTC_ALARM		S5PC1XX_IRQ_VIC0(28)
@@ -171,8 +171,15 @@
 #define IRQ_SDMIRQ		S5PC1XX_IRQ_VIC2(30)
 #define IRQ_SDMFIQ		S5PC1XX_IRQ_VIC2(31)
 
+#define IRQ_TIMER(x)		(IRQ_SDMFIQ + 1 + (x))
+#define IRQ_TIMER0		IRQ_TIMER(0)
+#define IRQ_TIMER1		IRQ_TIMER(1)
+#define IRQ_TIMER2		IRQ_TIMER(2)
+#define IRQ_TIMER3		IRQ_TIMER(3)
+#define IRQ_TIMER4		IRQ_TIMER(4)
+
 /* External interrupt */
-#define S3C_IRQ_EINT_BASE	(IRQ_SDMFIQ + 1)
+#define S3C_IRQ_EINT_BASE	(IRQ_SDMFIQ + 6)
 
 #define S3C_EINT(x)		(S3C_IRQ_EINT_BASE + (x - 16))
 #define IRQ_EINT(x)		(x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
index e44fd04..ae233bd 100644
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -20,77 +20,9 @@
 #include <asm/hardware/vic.h>
 
 #include <mach/map.h>
-#include <plat/regs-timer.h>
+#include <plat/irq-vic-timer.h>
 #include <plat/cpu.h>
 
-/* Timer interrupt handling */
-
-static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
-{
-	generic_handle_irq(sub_irq);
-}
-
-static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
-{
-	s3c_irq_demux_timer(irq, IRQ_TIMER0);
-}
-
-static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
-{
-	s3c_irq_demux_timer(irq, IRQ_TIMER1);
-}
-
-static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
-{
-	s3c_irq_demux_timer(irq, IRQ_TIMER2);
-}
-
-static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
-{
-	s3c_irq_demux_timer(irq, IRQ_TIMER3);
-}
-
-static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
-{
-	s3c_irq_demux_timer(irq, IRQ_TIMER4);
-}
-
-/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
-
-static void s3c_irq_timer_mask(unsigned int irq)
-{
-	u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-
-	reg &= 0x1f;  /* mask out pending interrupts */
-	reg &= ~(1 << (irq - IRQ_TIMER0));
-	__raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static void s3c_irq_timer_unmask(unsigned int irq)
-{
-	u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-
-	reg &= 0x1f;  /* mask out pending interrupts */
-	reg |= 1 << (irq - IRQ_TIMER0);
-	__raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static void s3c_irq_timer_ack(unsigned int irq)
-{
-	u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-
-	reg &= 0x1f;  /* mask out pending interrupts */
-	reg |= (1 << 5) << (irq - IRQ_TIMER0);
-	__raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static struct irq_chip s3c_irq_timer = {
-	.name		= "s3c-timer",
-	.mask		= s3c_irq_timer_mask,
-	.unmask		= s3c_irq_timer_unmask,
-	.ack		= s3c_irq_timer_ack,
-};
-
 struct uart_irq {
 	void __iomem	*regs;
 	unsigned int	 base_irq;
@@ -229,7 +161,7 @@ static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
 void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
 {
 	int i;
-	int uart, irq;
+	int uart;
 
 	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
@@ -240,17 +172,11 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
 
 	/* add the timer sub-irqs */
 
-	set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0);
-	set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1);
-	set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2);
-	set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3);
-	set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4);
-
-	for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
-		set_irq_chip(irq, &s3c_irq_timer);
-		set_irq_handler(irq, handle_level_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
+	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
+	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
+	s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
+	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
+	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
 
 	for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
 		s5pc1xx_uart_irq(&uart_irqs[uart]);
-- 
1.6.0.4

[PATCH] ARM: S5PC1XX: Use common UART IRQ handling code

[Ben Dooks]

From: Ben Dooks <ben-linux@fluff.org>

Use the common UART IRQ handling code for the S5PC100 system.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
 arch/arm/plat-s5pc1xx/Kconfig |    1 +
 arch/arm/plat-s5pc1xx/irq.c   |  116 +---------------------------------------
 2 files changed, 4 insertions(+), 113 deletions(-)

diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index 6438bcd..b7f442b 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -12,6 +12,7 @@ config PLAT_S5PC1XX
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select SAMSUNG_CLKSRC
+	select SAMSUNG_IRQ_UART
 	select SAMSUNG_IRQ_VIC_TIMER
 	select S3C_GPIO_TRACK
 	select S3C_GPIO_PULL_UPDOWN
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
index ae233bd..bfc5248 100644
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -21,18 +21,13 @@
 
 #include <mach/map.h>
 #include <plat/irq-vic-timer.h>
+#include <plat/irq-uart.h>
 #include <plat/cpu.h>
 
-struct uart_irq {
-	void __iomem	*regs;
-	unsigned int	 base_irq;
-	unsigned int	 parent_irq;
-};
-
 /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
  * are consecutive when looking up the interrupt in the demux routines.
  */
-static struct uart_irq uart_irqs[] = {
+static struct s3c_uart_irq uart_irqs[] = {
 	[0] = {
 		.regs		= (void *)S3C_VA_UART0,
 		.base_irq	= IRQ_S3CUART_BASE0,
@@ -55,113 +50,9 @@ static struct uart_irq uart_irqs[] = {
 	},
 };
 
-static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
-{
-	struct uart_irq *uirq = get_irq_chip_data(irq);
-	return uirq->regs;
-}
-
-static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
-{
-	return irq & 3;
-}
-
-/* UART interrupt registers, not worth adding to seperate include header */
-#define S3C64XX_UINTP	0x30
-#define S3C64XX_UINTSP	0x34
-#define S3C64XX_UINTM	0x38
-
-static void s3c_irq_uart_mask(unsigned int irq)
-{
-	void __iomem *regs = s3c_irq_uart_base(irq);
-	unsigned int bit = s3c_irq_uart_bit(irq);
-	u32 reg;
-
-	reg = __raw_readl(regs + S3C64XX_UINTM);
-	reg |= (1 << bit);
-	__raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_maskack(unsigned int irq)
-{
-	void __iomem *regs = s3c_irq_uart_base(irq);
-	unsigned int bit = s3c_irq_uart_bit(irq);
-	u32 reg;
-
-	reg = __raw_readl(regs + S3C64XX_UINTM);
-	reg |= (1 << bit);
-	__raw_writel(reg, regs + S3C64XX_UINTM);
-	__raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
-static void s3c_irq_uart_unmask(unsigned int irq)
-{
-	void __iomem *regs = s3c_irq_uart_base(irq);
-	unsigned int bit = s3c_irq_uart_bit(irq);
-	u32 reg;
-
-	reg = __raw_readl(regs + S3C64XX_UINTM);
-	reg &= ~(1 << bit);
-	__raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_ack(unsigned int irq)
-{
-	void __iomem *regs = s3c_irq_uart_base(irq);
-	unsigned int bit = s3c_irq_uart_bit(irq);
-
-	__raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
-static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
-{
-	struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
-	u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
-	int base = uirq->base_irq;
-
-	if (pend & (1 << 0))
-		generic_handle_irq(base);
-	if (pend & (1 << 1))
-		generic_handle_irq(base + 1);
-	if (pend & (1 << 2))
-		generic_handle_irq(base + 2);
-	if (pend & (1 << 3))
-		generic_handle_irq(base + 3);
-}
-
-static struct irq_chip s3c_irq_uart = {
-	.name		= "s3c-uart",
-	.mask		= s3c_irq_uart_mask,
-	.unmask		= s3c_irq_uart_unmask,
-	.mask_ack	= s3c_irq_uart_maskack,
-	.ack		= s3c_irq_uart_ack,
-};
-
-static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
-{
-	void __iomem *reg_base = uirq->regs;
-	unsigned int irq;
-	int offs;
-
-	/* mask all interrupts at the start. */
-	__raw_writel(0xf, reg_base + S3C64XX_UINTM);
-
-	for (offs = 0; offs < 3; offs++) {
-		irq = uirq->base_irq + offs;
-
-		set_irq_chip(irq, &s3c_irq_uart);
-		set_irq_chip_data(irq, uirq);
-		set_irq_handler(irq, handle_level_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
-
-	set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
-}
-
 void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
 {
 	int i;
-	int uart;
 
 	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
@@ -178,8 +69,7 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
 	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
 	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
 
-	for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
-		s5pc1xx_uart_irq(&uart_irqs[uart]);
+	s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
 }
 
 
-- 
1.6.0.4

RE: [PATCH] ARM: S5PC1XX: Move to using standard timer IRQ handling code

[Marek Szyprowski]

Hello,

On Tuesday, January 12, 2010 6:21 AM Ben Dooks wrote:

> Move to using the standard VIC/Timer IRQ handling code added previously\
> to avoid duplicating code.
> 
> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
> ---
>  arch/arm/mach-s5pc100/include/mach/tick.h |    2 +-
>  arch/arm/plat-s5pc1xx/Kconfig             |    2 +
>  arch/arm/plat-s5pc1xx/include/plat/irqs.h |   19 ++++--
>  arch/arm/plat-s5pc1xx/irq.c               |   88 ++--------------------------
>  4 files changed, 23 insertions(+), 88 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
> index d3de0f3..f338c9e 100644
> --- a/arch/arm/mach-s5pc100/include/mach/tick.h
> +++ b/arch/arm/mach-s5pc100/include/mach/tick.h
> @@ -21,7 +21,7 @@
>  static inline u32 s3c24xx_ostimer_pending(void)
>  {
>  	u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
> -	return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0));
> +	return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0));
>  }
> 
>  #define TICK_MAX	(0xffffffff)
> diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
> index 5d97b1c..6438bcd 100644
> --- a/arch/arm/plat-s5pc1xx/Kconfig
> +++ b/arch/arm/plat-s5pc1xx/Kconfig
> @@ -12,11 +12,13 @@ config PLAT_S5PC1XX
>  	select NO_IOPORT
>  	select ARCH_REQUIRE_GPIOLIB
>  	select SAMSUNG_CLKSRC
> +	select SAMSUNG_IRQ_VIC_TIMER
>  	select S3C_GPIO_TRACK
>  	select S3C_GPIO_PULL_UPDOWN
>  	select S3C_GPIO_CFG_S3C24XX
>  	select S3C_GPIO_CFG_S3C64XX
>  	select S5P_GPIO_CFG_S5PC1XX
> +	select SAMSUNG_IRQ_VIC_TIMER
>  	help
>  	  Base platform code for any Samsung S5PC1XX device

Double entry (probably a consequence of automatic merge or so).

> ...

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

RE: [PATCH] ARM: S5PC1XX: Use common UART IRQ handling code

[Marek Szyprowski]

Hello,

On Tuesday, January 12, 2010 6:21 AM Ben Dooks wrote:

> From: Ben Dooks <ben-linux@fluff.org>
> 
> Use the common UART IRQ handling code for the S5PC100 system.
> 
> Signed-off-by: Ben Dooks <ben-linux@fluff.org>

Tested and works fine on SMDKC100.

Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---
>  arch/arm/plat-s5pc1xx/Kconfig |    1 +
>  arch/arm/plat-s5pc1xx/irq.c   |  116 +---------------------------------------
>  2 files changed, 4 insertions(+), 113 deletions(-)
> 
> diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
> index 6438bcd..b7f442b 100644
> --- a/arch/arm/plat-s5pc1xx/Kconfig
> +++ b/arch/arm/plat-s5pc1xx/Kconfig
> @@ -12,6 +12,7 @@ config PLAT_S5PC1XX
>  	select NO_IOPORT
>  	select ARCH_REQUIRE_GPIOLIB
>  	select SAMSUNG_CLKSRC
> +	select SAMSUNG_IRQ_UART
>  	select SAMSUNG_IRQ_VIC_TIMER
>  	select S3C_GPIO_TRACK
>  	select S3C_GPIO_PULL_UPDOWN
> diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
> index ae233bd..bfc5248 100644
> --- a/arch/arm/plat-s5pc1xx/irq.c
> +++ b/arch/arm/plat-s5pc1xx/irq.c
> @@ -21,18 +21,13 @@
> 
>  #include <mach/map.h>
>  #include <plat/irq-vic-timer.h>
> +#include <plat/irq-uart.h>
>  #include <plat/cpu.h>
> 
> -struct uart_irq {
> -	void __iomem	*regs;
> -	unsigned int	 base_irq;
> -	unsigned int	 parent_irq;
> -};
> -
>  /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
>   * are consecutive when looking up the interrupt in the demux routines.
>   */
> -static struct uart_irq uart_irqs[] = {
> +static struct s3c_uart_irq uart_irqs[] = {
>  	[0] = {
>  		.regs		= (void *)S3C_VA_UART0,
>  		.base_irq	= IRQ_S3CUART_BASE0,
> @@ -55,113 +50,9 @@ static struct uart_irq uart_irqs[] = {
>  	},
>  };
> 
> -static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
> -{
> -	struct uart_irq *uirq = get_irq_chip_data(irq);
> -	return uirq->regs;
> -}
> -
> -static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
> -{
> -	return irq & 3;
> -}
> -
> -/* UART interrupt registers, not worth adding to seperate include header */
> -#define S3C64XX_UINTP	0x30
> -#define S3C64XX_UINTSP	0x34
> -#define S3C64XX_UINTM	0x38
> -
> -static void s3c_irq_uart_mask(unsigned int irq)
> -{
> -	void __iomem *regs = s3c_irq_uart_base(irq);
> -	unsigned int bit = s3c_irq_uart_bit(irq);
> -	u32 reg;
> -
> -	reg = __raw_readl(regs + S3C64XX_UINTM);
> -	reg |= (1 << bit);
> -	__raw_writel(reg, regs + S3C64XX_UINTM);
> -}
> -
> -static void s3c_irq_uart_maskack(unsigned int irq)
> -{
> -	void __iomem *regs = s3c_irq_uart_base(irq);
> -	unsigned int bit = s3c_irq_uart_bit(irq);
> -	u32 reg;
> -
> -	reg = __raw_readl(regs + S3C64XX_UINTM);
> -	reg |= (1 << bit);
> -	__raw_writel(reg, regs + S3C64XX_UINTM);
> -	__raw_writel(1 << bit, regs + S3C64XX_UINTP);
> -}
> -
> -static void s3c_irq_uart_unmask(unsigned int irq)
> -{
> -	void __iomem *regs = s3c_irq_uart_base(irq);
> -	unsigned int bit = s3c_irq_uart_bit(irq);
> -	u32 reg;
> -
> -	reg = __raw_readl(regs + S3C64XX_UINTM);
> -	reg &= ~(1 << bit);
> -	__raw_writel(reg, regs + S3C64XX_UINTM);
> -}
> -
> -static void s3c_irq_uart_ack(unsigned int irq)
> -{
> -	void __iomem *regs = s3c_irq_uart_base(irq);
> -	unsigned int bit = s3c_irq_uart_bit(irq);
> -
> -	__raw_writel(1 << bit, regs + S3C64XX_UINTP);
> -}
> -
> -static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
> -{
> -	struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
> -	u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
> -	int base = uirq->base_irq;
> -
> -	if (pend & (1 << 0))
> -		generic_handle_irq(base);
> -	if (pend & (1 << 1))
> -		generic_handle_irq(base + 1);
> -	if (pend & (1 << 2))
> -		generic_handle_irq(base + 2);
> -	if (pend & (1 << 3))
> -		generic_handle_irq(base + 3);
> -}
> -
> -static struct irq_chip s3c_irq_uart = {
> -	.name		= "s3c-uart",
> -	.mask		= s3c_irq_uart_mask,
> -	.unmask		= s3c_irq_uart_unmask,
> -	.mask_ack	= s3c_irq_uart_maskack,
> -	.ack		= s3c_irq_uart_ack,
> -};
> -
> -static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
> -{
> -	void __iomem *reg_base = uirq->regs;
> -	unsigned int irq;
> -	int offs;
> -
> -	/* mask all interrupts at the start. */
> -	__raw_writel(0xf, reg_base + S3C64XX_UINTM);
> -
> -	for (offs = 0; offs < 3; offs++) {
> -		irq = uirq->base_irq + offs;
> -
> -		set_irq_chip(irq, &s3c_irq_uart);
> -		set_irq_chip_data(irq, uirq);
> -		set_irq_handler(irq, handle_level_irq);
> -		set_irq_flags(irq, IRQF_VALID);
> -	}
> -
> -	set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
> -}
> -
>  void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
>  {
>  	int i;
> -	int uart;
> 
>  	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
> 
> @@ -178,8 +69,7 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
>  	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
>  	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
> 
> -	for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
> -		s5pc1xx_uart_irq(&uart_irqs[uart]);
> +	s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
>  }
> 
> 
> --
> 1.6.0.4


Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

RE: [PATCH] ARM: S5PC1XX: Move to using standard timer IRQ handling code

[Marek Szyprowski]

Hello,

On Tuesday, January 12, 2010 6:21 AM Ben Dooks wrote:

> From: Ben Dooks <ben-linux@fluff.org>
> 
> Move to using the standard VIC/Timer IRQ handling code added previously\
> to avoid duplicating code.
> 
> Signed-off-by: Ben Dooks <ben-linux@fluff.org>

Tested and works fine on SMDKC100.

Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---
>  arch/arm/mach-s5pc100/include/mach/tick.h |    2 +-
>  arch/arm/plat-s5pc1xx/Kconfig             |    2 +
>  arch/arm/plat-s5pc1xx/include/plat/irqs.h |   19 ++++--
>  arch/arm/plat-s5pc1xx/irq.c               |   88 ++--------------------------
>  4 files changed, 23 insertions(+), 88 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
> index d3de0f3..f338c9e 100644
> --- a/arch/arm/mach-s5pc100/include/mach/tick.h
> +++ b/arch/arm/mach-s5pc100/include/mach/tick.h
> @@ -21,7 +21,7 @@
>  static inline u32 s3c24xx_ostimer_pending(void)
>  {
>  	u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
> -	return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0));
> +	return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0));
>  }
> 
>  #define TICK_MAX	(0xffffffff)
> diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
> index 5d97b1c..6438bcd 100644
> --- a/arch/arm/plat-s5pc1xx/Kconfig
> +++ b/arch/arm/plat-s5pc1xx/Kconfig
> @@ -12,11 +12,13 @@ config PLAT_S5PC1XX
>  	select NO_IOPORT
>  	select ARCH_REQUIRE_GPIOLIB
>  	select SAMSUNG_CLKSRC
> +	select SAMSUNG_IRQ_VIC_TIMER
>  	select S3C_GPIO_TRACK
>  	select S3C_GPIO_PULL_UPDOWN
>  	select S3C_GPIO_CFG_S3C24XX
>  	select S3C_GPIO_CFG_S3C64XX
>  	select S5P_GPIO_CFG_S5PC1XX
> +	select SAMSUNG_IRQ_VIC_TIMER
>  	help
>  	  Base platform code for any Samsung S5PC1XX device
> 
> diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
> index ef87363..409c804 100644
> --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
> +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
> @@ -88,11 +88,11 @@
>  #define IRQ_MDMA		S5PC1XX_IRQ_VIC0(18)
>  #define IRQ_PDMA0		S5PC1XX_IRQ_VIC0(19)
>  #define IRQ_PDMA1		S5PC1XX_IRQ_VIC0(20)
> -#define IRQ_TIMER0		S5PC1XX_IRQ_VIC0(21)
> -#define IRQ_TIMER1		S5PC1XX_IRQ_VIC0(22)
> -#define IRQ_TIMER2		S5PC1XX_IRQ_VIC0(23)
> -#define IRQ_TIMER3		S5PC1XX_IRQ_VIC0(24)
> -#define IRQ_TIMER4		S5PC1XX_IRQ_VIC0(25)
> +#define IRQ_TIMER0_VIC		S5PC1XX_IRQ_VIC0(21)
> +#define IRQ_TIMER1_VIC		S5PC1XX_IRQ_VIC0(22)
> +#define IRQ_TIMER2_VIC		S5PC1XX_IRQ_VIC0(23)
> +#define IRQ_TIMER3_VIC		S5PC1XX_IRQ_VIC0(24)
> +#define IRQ_TIMER4_VIC		S5PC1XX_IRQ_VIC0(25)
>  #define IRQ_SYSTIMER		S5PC1XX_IRQ_VIC0(26)
>  #define IRQ_WDT			S5PC1XX_IRQ_VIC0(27)
>  #define IRQ_RTC_ALARM		S5PC1XX_IRQ_VIC0(28)
> @@ -171,8 +171,15 @@
>  #define IRQ_SDMIRQ		S5PC1XX_IRQ_VIC2(30)
>  #define IRQ_SDMFIQ		S5PC1XX_IRQ_VIC2(31)
> 
> +#define IRQ_TIMER(x)		(IRQ_SDMFIQ + 1 + (x))
> +#define IRQ_TIMER0		IRQ_TIMER(0)
> +#define IRQ_TIMER1		IRQ_TIMER(1)
> +#define IRQ_TIMER2		IRQ_TIMER(2)
> +#define IRQ_TIMER3		IRQ_TIMER(3)
> +#define IRQ_TIMER4		IRQ_TIMER(4)
> +
>  /* External interrupt */
> -#define S3C_IRQ_EINT_BASE	(IRQ_SDMFIQ + 1)
> +#define S3C_IRQ_EINT_BASE	(IRQ_SDMFIQ + 6)
> 
>  #define S3C_EINT(x)		(S3C_IRQ_EINT_BASE + (x - 16))
>  #define IRQ_EINT(x)		(x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
> diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
> index e44fd04..ae233bd 100644
> --- a/arch/arm/plat-s5pc1xx/irq.c
> +++ b/arch/arm/plat-s5pc1xx/irq.c
> @@ -20,77 +20,9 @@
>  #include <asm/hardware/vic.h>
> 
>  #include <mach/map.h>
> -#include <plat/regs-timer.h>
> +#include <plat/irq-vic-timer.h>
>  #include <plat/cpu.h>
> 
> -/* Timer interrupt handling */
> -
> -static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
> -{
> -	generic_handle_irq(sub_irq);
> -}
> -
> -static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
> -{
> -	s3c_irq_demux_timer(irq, IRQ_TIMER0);
> -}
> -
> -static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
> -{
> -	s3c_irq_demux_timer(irq, IRQ_TIMER1);
> -}
> -
> -static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
> -{
> -	s3c_irq_demux_timer(irq, IRQ_TIMER2);
> -}
> -
> -static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
> -{
> -	s3c_irq_demux_timer(irq, IRQ_TIMER3);
> -}
> -
> -static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
> -{
> -	s3c_irq_demux_timer(irq, IRQ_TIMER4);
> -}
> -
> -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
> -
> -static void s3c_irq_timer_mask(unsigned int irq)
> -{
> -	u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
> -
> -	reg &= 0x1f;  /* mask out pending interrupts */
> -	reg &= ~(1 << (irq - IRQ_TIMER0));
> -	__raw_writel(reg, S3C64XX_TINT_CSTAT);
> -}
> -
> -static void s3c_irq_timer_unmask(unsigned int irq)
> -{
> -	u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
> -
> -	reg &= 0x1f;  /* mask out pending interrupts */
> -	reg |= 1 << (irq - IRQ_TIMER0);
> -	__raw_writel(reg, S3C64XX_TINT_CSTAT);
> -}
> -
> -static void s3c_irq_timer_ack(unsigned int irq)
> -{
> -	u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
> -
> -	reg &= 0x1f;  /* mask out pending interrupts */
> -	reg |= (1 << 5) << (irq - IRQ_TIMER0);
> -	__raw_writel(reg, S3C64XX_TINT_CSTAT);
> -}
> -
> -static struct irq_chip s3c_irq_timer = {
> -	.name		= "s3c-timer",
> -	.mask		= s3c_irq_timer_mask,
> -	.unmask		= s3c_irq_timer_unmask,
> -	.ack		= s3c_irq_timer_ack,
> -};
> -
>  struct uart_irq {
>  	void __iomem	*regs;
>  	unsigned int	 base_irq;
> @@ -229,7 +161,7 @@ static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
>  void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
>  {
>  	int i;
> -	int uart, irq;
> +	int uart;
> 
>  	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
> 
> @@ -240,17 +172,11 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
> 
>  	/* add the timer sub-irqs */
> 
> -	set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0);
> -	set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1);
> -	set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2);
> -	set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3);
> -	set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4);
> -
> -	for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
> -		set_irq_chip(irq, &s3c_irq_timer);
> -		set_irq_handler(irq, handle_level_irq);
> -		set_irq_flags(irq, IRQF_VALID);
> -	}
> +	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
> +	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
> +	s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
> +	s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
> +	s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
> 
>  	for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
>  		s5pc1xx_uart_irq(&uart_irqs[uart]);
> --
> 1.6.0.4
> 


Best regards
--
Marek Szyprowski
Samsung Poland R&D Center

Re: [PATCH] ARM: S5PC1XX: Move to using standard timer IRQ handling code

[Ben Dooks]

Ok, thanks for the testing.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.