[PATCH 3/3] MIPS: deal with larger physical offsets

[PATCH 3/3] MIPS: deal with larger physical offsets

[Florian Fainelli]

AR7 has a larger physical offset than other MIPS based
systems and therefore needs to setup its handlers beyond
the usual KSEG0 range. When running the kernel in mapped
mode this modification is also required. Remove function
comment which is now incorrect.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 574608e..14d515f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -50,6 +50,7 @@
 #include <asm/types.h>
 #include <asm/stacktrace.h>
 #include <asm/irq.h>
+#include <asm/uasm.h>
 
 extern void check_wait(void);
 extern asmlinkage void r4k_wait(void);
@@ -1271,11 +1272,6 @@ unsigned long ebase;
 unsigned long exception_handlers[32];
 unsigned long vi_handlers[64];
 
-/*
- * As a side effect of the way this is implemented we're limited
- * to interrupt handlers in the address range from
- * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
- */
 void __init *set_except_vector(int n, void *addr)
 {
 	unsigned long handler = (unsigned long) addr;
@@ -1283,9 +1279,18 @@ void __init *set_except_vector(int n, void *addr)
 
 	exception_handlers[n] = handler;
 	if (n == 0 && cpu_has_divec) {
-		*(u32 *)(ebase + 0x200) = 0x08000000 |
-					  (0x03ffffff & (handler >> 2));
-		local_flush_icache_range(ebase + 0x200, ebase + 0x204);
+		unsigned long jump_mask = ~((1 << 28) - 1);
+		u32 *buf = (u32 *)(ebase + 0x200);
+		unsigned int k0 = 26;
+		if((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
+			uasm_i_j(&buf, handler & jump_mask);
+			uasm_i_nop(&buf);
+		} else {
+			UASM_i_LA(&buf, k0, handler);
+			uasm_i_jr(&buf, k0);
+			uasm_i_nop(&buf);
+		}
+		local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
 	}
 	return (void *)old_handler;
 }

Re: [PATCH 3/3] MIPS: deal with larger physical offsets

[Ralf Baechle]

On Thu, Jan 28, 2010 at 03:22:37PM +0100, Florian Fainelli wrote:

Thanks, queued for 2.6.34.

  Ral

Re: [PATCH 3/3] MIPS: deal with larger physical offsets

[Sergei Shtylyov]

Florian Fainelli wrote:
> AR7 has a larger physical offset than other MIPS based
> systems and therefore needs to setup its handlers beyond
> the usual KSEG0 range. When running the kernel in mapped
> mode this modification is also required. Remove function
> comment which is now incorrect.
>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru>
> Signed-off-by: Florian Fainelli <florian@openwrt.org>
> ---
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 574608e..14d515f 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
...]
> @@ -1283,9 +1279,18 @@ void __init *set_except_vector(int n, void *addr)
>  
>  	exception_handlers[n] = handler;
>  	if (n == 0 && cpu_has_divec) {
> -		*(u32 *)(ebase + 0x200) = 0x08000000 |
> -					  (0x03ffffff & (handler >> 2));
> -		local_flush_icache_range(ebase + 0x200, ebase + 0x204);
> +		unsigned long jump_mask = ~((1 << 28) - 1);
> +		u32 *buf = (u32 *)(ebase + 0x200);
> +		unsigned int k0 = 26;
> +		if((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
>   

  Missing space after *if* (should be easy for Ralf to fix manually 
though). You should run the patch thru scripts/checkpatch.pl first.

WBR, Sergei

Re: [PATCH 3/3] MIPS: deal with larger physical offsets

[Ralf Baechle]

On Thu, Jan 28, 2010 at 07:37:33PM +0300, Sergei Shtylyov wrote:

> Florian Fainelli wrote:
> >AR7 has a larger physical offset than other MIPS based
> >systems and therefore needs to setup its handlers beyond
> >the usual KSEG0 range. When running the kernel in mapped
> >mode this modification is also required. Remove function
> >comment which is now incorrect.
> >
> >Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> >Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru>
> >Signed-off-by: Florian Fainelli <florian@openwrt.org>
> >---
> >diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> >index 574608e..14d515f 100644
> >--- a/arch/mips/kernel/traps.c
> >+++ b/arch/mips/kernel/traps.c
> ...]
> >@@ -1283,9 +1279,18 @@ void __init *set_except_vector(int n, void *addr)
> > 	exception_handlers[n] = handler;
> > 	if (n == 0 && cpu_has_divec) {
> >-		*(u32 *)(ebase + 0x200) = 0x08000000 |
> >-					  (0x03ffffff & (handler >> 2));
> >-		local_flush_icache_range(ebase + 0x200, ebase + 0x204);
> >+		unsigned long jump_mask = ~((1 << 28) - 1);
> >+		u32 *buf = (u32 *)(ebase + 0x200);
> >+		unsigned int k0 = 26;
> >+		if((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
> 
>  Missing space after *if* (should be easy for Ralf to fix manually
> though). You should run the patch thru scripts/checkpatch.pl first.

Just did that.  Thanks for nitpicking :-)

  Ralf

Re: [PATCH 3/3] MIPS: deal with larger physical offsets

[Maxime Bizon]

On Thu, 2010-01-28 at 15:22 +0100, Florian Fainelli wrote:

Hi,

>  	if (n == 0 && cpu_has_divec) {
> -		*(u32 *)(ebase + 0x200) = 0x08000000 |
> -					  (0x03ffffff & (handler >> 2));
> -		local_flush_icache_range(ebase + 0x200, ebase + 0x204);
> +		unsigned long jump_mask = ~((1 << 28) - 1);
> +		u32 *buf = (u32 *)(ebase + 0x200);
> +		unsigned int k0 = 26;
> +		if((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
> +			uasm_i_j(&buf, handler & jump_mask);
> +			uasm_i_nop(&buf);

This results in "Micro-assembler field overflow" on my board.

jump_mask is 0xf0000000, so I guess you meant:

-                       uasm_i_j(&buf, handler & jump_mask);
+                       uasm_i_j(&buf, handler & ~jump_mask);


And by the way, shouldn't jump_mask be 0xfc000000 ?

-- 
Maxime