Re: [RFC][PATCH 06/11] perf, x86: PEBS infrastructure

[Robert Richter <robert.richter@amd.com>]

On 03.03.10 17:39:42, Peter Zijlstra wrote:
> Implement a simple PEBS model that always takes a single PEBS event at
> a time. This is done so that the interaction with the rest of the
> system is as expected (freq adjust, period randomization, lbr).
> 
> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
> ---

[...]

> +static int validate_event(struct perf_event *event)
> +{
> +	struct cpu_hw_events *fake_cpuc;
> +	struct event_constraint *c;
> +	int ret = 0;
> +
> +	fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
> +	if (!fake_cpuc)
> +		return -ENOMEM;
> +
> +	c = x86_pmu.get_event_constraints(fake_cpuc, event);
> +
> +	if (!c || !c->weight)
> +		ret = -ENOSPC;
> +
> +	if (x86_pmu.put_event_constraints)
> +		x86_pmu.put_event_constraints(fake_cpuc, event);

A fake cpu with the struct filled with zeros will cause a null pointer
exception in amd_get_event_constraints():

	struct amd_nb *nb = cpuc->amd_nb;

Shouldn't x86_schedule_events() sufficient to decide if a single
counter is available? I did not yet look at group events, this might
happen there too.

-Robert

> +
> +	kfree(fake_cpuc);
> +
> +	return ret;
> +}
> +
> +/*
>   * validate a single event group
>   *
>   * validation include:
> @@ -1495,6 +1426,8 @@ const struct pmu *hw_perf_event_init(str
>  
>  		if (event->group_leader != event)
>  			err = validate_group(event);
> +		else
> +			err = validate_event(event);
>  
>  		event->pmu = tmp;
>  	}

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com