[PATCH 0/2] ASoC: tlv320dac33: DSP mode and clocking updates

[PATCH 0/2] ASoC: tlv320dac33: DSP mode and clocking updates

[Peter Ujfalusi]

Hello,

tlv320dac33 can not support DSP_B mode since the data delay can not be set to be
actually 0. Only DSP_A mode can be supported, so fix the DSP_A mode, and remove
the DSP_B.

The original internal clock distribution config has been found to be not
optimal, so fix that as well.

Peter

---
Peter Ujfalusi (2):
  ASoC: tlv320dac33: Fix DSP modes
  ASoC: tlv320dac33: Internal clocking changes

 sound/soc/codecs/tlv320dac33.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

[PATCH 1/2] ASoC: tlv320dac33: Fix DSP modes

[Peter Ujfalusi]

To make DSP_A mode working correctly the data delay should be
configured to 0. DSP_B mode thus can not be used with DAC33,
so remove it.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
---
 sound/soc/codecs/tlv320dac33.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index a6f1927..f5dbed2 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -1028,11 +1028,7 @@ static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
 	case SND_SOC_DAIFMT_DSP_A:
 		aictrl_a |= DAC33_AFMT_DSP;
 		aictrl_b &= ~DAC33_DATA_DELAY_MASK;
-		aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
-		break;
-	case SND_SOC_DAIFMT_DSP_B:
-		aictrl_a |= DAC33_AFMT_DSP;
-		aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
+		aictrl_b |= DAC33_DATA_DELAY(0);
 		break;
 	case SND_SOC_DAIFMT_RIGHT_J:
 		aictrl_a |= DAC33_AFMT_RIGHT_J;
-- 
1.7.0.2

[PATCH 2/2] ASoC: tlv320dac33: Internal clocking changes

[Peter Ujfalusi]

During validation of the internal clocking setup it has
been found that the following settings were not configured
in an optimal way:

ASRC_CTRL_A: SRCLKDIV was incorrect, instad of divide ratio 3,
             ratio of 2 has to be used (as the comment stated)
DAC_CTRL_A: Fs = Fsref is the desired configuration instead of
            Fs = Fsref / 1.5

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
---
 sound/soc/codecs/tlv320dac33.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index f5dbed2..ee2e1e3 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -762,7 +762,7 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 	if (dac33->fifo_mode) {
 		/* Generic for all FIFO modes */
 		/* 50-51 : ASRC Control registers */
-		dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
+		dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 		dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 
 		/* Write registers 0x34 and 0x35 (MSB, LSB) */
@@ -1052,7 +1052,7 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
 {
 	/* 44-46: DAC Control Registers */
 	/* A : DAC sample rate Fsref/1.5 */
-	dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
+	dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 	/* B : DAC src=normal, not muted */
 	dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 					     DAC33_DACSRCL_LEFT);
-- 
1.7.0.2

Re: [PATCH 0/2] ASoC: tlv320dac33: DSP mode and clocking updates

[Liam Girdwood]

On Fri, 2010-03-19 at 11:10 +0200, Peter Ujfalusi wrote:
> Hello,
> 
> tlv320dac33 can not support DSP_B mode since the data delay can not be set to be
> actually 0. Only DSP_A mode can be supported, so fix the DSP_A mode, and remove
> the DSP_B.
> 
> The original internal clock distribution config has been found to be not
> optimal, so fix that as well.
> 

Both

Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>

-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk

Re: [PATCH 0/2] ASoC: tlv320dac33: DSP mode and clocking updates

[Mark Brown]

On Fri, Mar 19, 2010 at 09:38:03AM +0000, Liam Girdwood wrote:
> On Fri, 2010-03-19 at 11:10 +0200, Peter Ujfalusi wrote:

> > tlv320dac33 can not support DSP_B mode since the data delay can not be set to be
> > actually 0. Only DSP_A mode can be supported, so fix the DSP_A mode, and remove
> > the DSP_B.

> > The original internal clock distribution config has been found to be not
> > optimal, so fix that as well.

> Both

> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>

...and applied for 2.6.34, thanks.