* [PATCH] x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs
@ 2010-04-27 10:13 Andreas Herrmann
2010-05-13 23:39 ` [tip:x86/urgent] " tip-bot for Andreas Herrmann
0 siblings, 1 reply; 2+ messages in thread
From: Andreas Herrmann @ 2010-04-27 10:13 UTC (permalink / raw)
To: H. Peter Anvin, Ingo Molnar, Thomas Gleixner; +Cc: linux-kernel
If host CPU is exposed to a guest the OSVW MSRs are not guaranteed
to be present and a GP fault occurs. Thus checking the feature flag is
essential.
Cc: <stable@kernel.org> # .32.x .33.x
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
arch/x86/kernel/process.c | 12 +++++++-----
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 28ad9f4..0415c3e 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -546,11 +546,13 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
* check OSVW bit for CPUs that are not affected
* by erratum #400
*/
- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
- if (val >= 2) {
- rdmsrl(MSR_AMD64_OSVW_STATUS, val);
- if (!(val & BIT(1)))
- goto no_c1e_idle;
+ if (cpu_has(c, X86_FEATURE_OSVW)) {
+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
+ if (val >= 2) {
+ rdmsrl(MSR_AMD64_OSVW_STATUS, val);
+ if (!(val & BIT(1)))
+ goto no_c1e_idle;
+ }
}
return 1;
}
--
1.6.4.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [tip:x86/urgent] x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs
2010-04-27 10:13 [PATCH] x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs Andreas Herrmann
@ 2010-05-13 23:39 ` tip-bot for Andreas Herrmann
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot for Andreas Herrmann @ 2010-05-13 23:39 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, andreas.herrmann3, herrmann.der.user,
tglx, hpa
Commit-ID: f01487119dda3d9f58c9729c7361ecc50a61c188
Gitweb: http://git.kernel.org/tip/f01487119dda3d9f58c9729c7361ecc50a61c188
Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
AuthorDate: Tue, 27 Apr 2010 12:13:48 +0200
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Thu, 13 May 2010 16:21:20 -0700
x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs
If host CPU is exposed to a guest the OSVW MSRs are not guaranteed
to be present and a GP fault occurs. Thus checking the feature flag is
essential.
Cc: <stable@kernel.org> # .32.x .33.x
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100427101348.GC4489@alberich.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/kernel/process.c | 12 +++++++-----
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 28ad9f4..0415c3e 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -546,11 +546,13 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
* check OSVW bit for CPUs that are not affected
* by erratum #400
*/
- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
- if (val >= 2) {
- rdmsrl(MSR_AMD64_OSVW_STATUS, val);
- if (!(val & BIT(1)))
- goto no_c1e_idle;
+ if (cpu_has(c, X86_FEATURE_OSVW)) {
+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
+ if (val >= 2) {
+ rdmsrl(MSR_AMD64_OSVW_STATUS, val);
+ if (!(val & BIT(1)))
+ goto no_c1e_idle;
+ }
}
return 1;
}
^ permalink raw reply related [flat|nested] 2+ messages in thread
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2010-04-27 10:13 [PATCH] x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs Andreas Herrmann
2010-05-13 23:39 ` [tip:x86/urgent] " tip-bot for Andreas Herrmann
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