From: Li Peng <peng.li@linux.intel.com>
To: Zhenyu Wang <zhenyuw@linux.intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Add CxSR support on Pineview DDR3
Date: Tue, 18 May 2010 18:24:23 +0800 [thread overview]
Message-ID: <20100518102423.GA14910@pli1.bj.intel.com> (raw)
In-Reply-To: <20100517092638.GB19057@zhen-devel.sh.intel.com>
On Mon, May 17, 2010 at 05:26:38PM +0800, Zhenyu Wang wrote:
> On 2010.05.17 22:07:30 +0800, Li Peng wrote:
> > Pineview with DDR3 memory has different latencies to enable CxSR.
> > This patch updates CxSR latency table to add Pineview DDR3 latency
> > configuration. It also adds one flag "is_ddr3" for checking DDR3
> > setting in MCHBAR.
> >
>
> This is not against drm-intel-next? which has commit d4294342f to
> cleanup wm setup for pineview.
>
Thanks for the reminder. The patch is against mainline.
I will rebase it to drm-intel-next.
Peng
> --
> Open Source Technology Center, Intel ltd.
>
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
prev parent reply other threads:[~2010-05-18 2:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-17 14:07 [PATCH] drm/i915: Add CxSR support on Pineview DDR3 Li Peng
2010-05-17 9:26 ` Zhenyu Wang
2010-05-18 10:24 ` Li Peng [this message]
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