[PATCH] A workaround for AMD erratum 411

[Wei Wang2 <wei.wang2@amd.com>]

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Hi,
This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does 
not cause functional issues but may reduce the power saving effectiveness of 
message-triggered C1e mode. This would normally occur only if OS which has 
used the local APIC timer masks the interrupt without clearing Timer Initial 
Count Register.

Thanks,
Wei

Signed-off-by: Wei Wang <wei.wang2@amd.com>
-- 
AMD GmbH, Germany
Operating System Research Center

Legal Information:
Advanced Micro Devices GmbH
Karl-Hammerschmidt-Str. 34
85609 Dornach b. München

Geschäftsführer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni
Sitz: Dornach, Gemeinde Aschheim, Landkreis München
Registergericht München, HRB Nr. 43632

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diff -r e6f751ed8e38 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c	Tue Mar 09 10:00:37 2010 +0000
+++ b/xen/arch/x86/apic.c	Fri May 28 12:28:22 2010 +0200
@@ -209,6 +209,11 @@ void clear_local_APIC(void)
      */
     v = apic_read(APIC_LVTT);
     apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+
+    /* Workaround AMD Erratum 411. Please refer to AMD
+    revision guide for more details. */
+    apic_write_around(APIC_TMICT, 0x0);
+
     v = apic_read(APIC_LVT0);
     apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
     v = apic_read(APIC_LVT1);
@@ -1187,6 +1192,10 @@ void disable_APIC_timer(void)
         
         v = apic_read(APIC_LVTT);
         apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+
+        /* Workaround AMD Erratum 411. Please refer to AMD
+        revision guide for more details. */
+        apic_write_around(APIC_TMICT, 0x0);
     }
 }
 

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