* [PATCH] A workaround for AMD erratum 411
@ 2010-06-04 11:33 Wei Wang2
2010-06-04 12:31 ` Keir Fraser
0 siblings, 1 reply; 2+ messages in thread
From: Wei Wang2 @ 2010-06-04 11:33 UTC (permalink / raw)
To: xen-devel@lists.xensource.com
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Hi,
This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does
not cause functional issues but may reduce the power saving effectiveness of
message-triggered C1e mode. This would normally occur only if OS which has
used the local APIC timer masks the interrupt without clearing Timer Initial
Count Register.
Thanks,
Wei
Signed-off-by: Wei Wang <wei.wang2@amd.com>
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[-- Attachment #2: erratum411.patch --]
[-- Type: text/x-diff, Size: 882 bytes --]
diff -r e6f751ed8e38 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c Tue Mar 09 10:00:37 2010 +0000
+++ b/xen/arch/x86/apic.c Fri May 28 12:28:22 2010 +0200
@@ -209,6 +209,11 @@ void clear_local_APIC(void)
*/
v = apic_read(APIC_LVTT);
apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+
+ /* Workaround AMD Erratum 411. Please refer to AMD
+ revision guide for more details. */
+ apic_write_around(APIC_TMICT, 0x0);
+
v = apic_read(APIC_LVT0);
apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
v = apic_read(APIC_LVT1);
@@ -1187,6 +1192,10 @@ void disable_APIC_timer(void)
v = apic_read(APIC_LVTT);
apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
+
+ /* Workaround AMD Erratum 411. Please refer to AMD
+ revision guide for more details. */
+ apic_write_around(APIC_TMICT, 0x0);
}
}
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^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH] A workaround for AMD erratum 411
2010-06-04 11:33 [PATCH] A workaround for AMD erratum 411 Wei Wang2
@ 2010-06-04 12:31 ` Keir Fraser
0 siblings, 0 replies; 2+ messages in thread
From: Keir Fraser @ 2010-06-04 12:31 UTC (permalink / raw)
To: Wei Wang2, xen-devel@lists.xensource.com
I don't think we are susceptible to this bug, but it's probably a nice thing
to do anyway. I will apply some variant of it to xen-unstable at least.
-- Keir
On 04/06/2010 12:33, "Wei Wang2" <wei.wang2@amd.com> wrote:
> Hi,
> This patch is a workaround of AMD erratum 411 for family 10h CPUs. This does
> not cause functional issues but may reduce the power saving effectiveness of
> message-triggered C1e mode. This would normally occur only if OS which has
> used the local APIC timer masks the interrupt without clearing Timer Initial
> Count Register.
>
> Thanks,
> Wei
>
> Signed-off-by: Wei Wang <wei.wang2@amd.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2010-06-04 11:33 [PATCH] A workaround for AMD erratum 411 Wei Wang2
2010-06-04 12:31 ` Keir Fraser
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