From: Aurelien Jarno <aurelien@aurel32.net>
To: Nathan Froyd <froydnj@codesourcery.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 5/8] target-mips: add microMIPS CPUs
Date: Wed, 9 Jun 2010 16:02:29 +0200 [thread overview]
Message-ID: <20100609140229.GD26968@volta.aurel32.net> (raw)
In-Reply-To: <1276029003-10158-6-git-send-email-froydnj@codesourcery.com>
On Tue, Jun 08, 2010 at 01:30:00PM -0700, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
> target-mips/translate_init.c | 61 ++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 61 insertions(+), 0 deletions(-)
>
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index b79ed56..8e17f4b 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -141,6 +141,25 @@ static const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_FMT,
> },
> {
> + .name = "4Km-micromips",
> + .CP0_PRid = 0x00018300,
> + /* Config1 implemented, fixed mapping MMU,
> + no virtual icache, uncached coherency. */
> + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 |
> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x1258FF17,
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> + .mmu_type = MMU_TYPE_FMT,
> + },
> + {
> .name = "4KEcR1",
> .CP0_PRid = 0x00018400,
> .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
> @@ -245,6 +264,25 @@ static const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_R4000,
> },
> {
> + .name = "24Kc-micromips",
> + .CP0_PRid = 0x00019300,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + /* No DSP implemented. */
> + .CP0_Status_rw_bitmask = 0x1278FF1F,
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> + {
> .name = "24Kf",
> .CP0_PRid = 0x00019300,
> .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> @@ -269,6 +307,29 @@ static const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_R4000,
> },
> {
> + .name = "24Kf-micromips",
> + .CP0_PRid = 0x00019300,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 4,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + /* No DSP implemented. */
> + .CP0_Status_rw_bitmask = 0x3678FF1F,
> + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
> + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> + {
> .name = "34Kf",
> .CP0_PRid = 0x00019500,
> .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
None of those CPU seems to be real CPU. According to the MIPS website
(which BTW has very few details about microMIPS), the microMIPS ASE is
implemented in the M14K core, which seems to be a 4K core with R2 and
microMIPS support. Wouldn't it be better to add this one instead?
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2010-06-09 14:02 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-08 20:29 [Qemu-devel] [PATCH 0/8] target-mips: add microMIPS ASE support, v3 Nathan Froyd
2010-06-08 20:29 ` [Qemu-devel] [PATCH 1/8] target-mips: define constants for magic numbers Nathan Froyd
2010-06-08 20:29 ` [Qemu-devel] [PATCH 2/8] target-mips: refactor c{, abs}.cond.fmt insns Nathan Froyd
2010-06-08 20:29 ` [Qemu-devel] [PATCH 3/8] target-mips: mips16 cleanups Nathan Froyd
2010-06-08 20:29 ` [Qemu-devel] [PATCH 4/8] target-mips: microMIPS ASE support Nathan Froyd
2010-06-09 14:08 ` Aurelien Jarno
2010-06-08 20:30 ` [Qemu-devel] [PATCH 5/8] target-mips: add microMIPS CPUs Nathan Froyd
2010-06-09 14:02 ` Aurelien Jarno [this message]
2010-06-08 20:30 ` [Qemu-devel] [PATCH 6/8] target-mips: add microMIPS exception handler support Nathan Froyd
2010-06-08 20:30 ` [Qemu-devel] [PATCH 7/8] linux-user: honor low bit of entry PC for MIPS Nathan Froyd
2010-06-08 20:30 ` [Qemu-devel] [PATCH 8/8] hw: honor low bit in mipssim machine Nathan Froyd
2010-06-09 14:10 ` [Qemu-devel] [PATCH 0/8] target-mips: add microMIPS ASE support, v3 Aurelien Jarno
2010-06-09 15:39 ` Nathan Froyd
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