From: Mark Brown <broonie@opensource.wolfsonmicro.com>
To: Jassi Brar <jassisinghbrar@gmail.com>
Cc: alsa-devel@alsa-project.org,
Seungwhan Youn <claude.youn@gmail.com>,
Liam Girdwood <lrg@slimlogic.co.uk>,
Seungwhan Youn <sw.youn@samsung.com>
Subject: Re: [PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting
Date: Fri, 6 Aug 2010 11:19:18 +0100 [thread overview]
Message-ID: <20100806101918.GB398@rakim.wolfsonmicro.main> (raw)
In-Reply-To: <AANLkTingw3AiJdN1_tahFbmHNWeqMZnb6HB0r=PuK20f@mail.gmail.com>
On Fri, Aug 06, 2010 at 01:27:48PM +0900, Jassi Brar wrote:
> This is OK. Though I don't remember why it wasn't accepted when
> I submitted a few months ago.
IIRC it was part of a larger patch or patch series which had other
issues.
next prev parent reply other threads:[~2010-08-06 10:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-06 0:13 [PATCH 0/5] ASoC: Fix smdk64xx-wm8580 problems Seungwhan Youn
2010-08-06 0:18 ` [PATCH 1/5] ASoC: wm8580: Add to support ADC clock source setting Seungwhan Youn
2010-08-06 4:27 ` Jassi Brar
2010-08-06 10:19 ` Mark Brown [this message]
2010-08-08 1:15 ` Jassi Brar
2010-08-06 0:21 ` [PATCH 2/5] ASoC: S3C64XX: Add ADC source clock setting Seungwhan Youn
2010-08-06 10:26 ` Mark Brown
2010-08-06 16:28 ` Seungwhan Youn
2010-08-06 16:49 ` Mark Brown
2010-08-06 17:00 ` Seungwhan Youn
2010-08-06 0:26 ` [PATCH 3/5] ASoC: wm8580: Fix Master Mode BCLK rates names Seungwhan Youn
2010-08-06 0:32 ` [PATCH 4/5] ASoC: wm8580: Add to support Master Mode Rates Seungwhan Youn
2010-08-06 4:32 ` Jassi Brar
2010-08-06 5:54 ` Seungwhan Youn
2010-08-06 0:36 ` [PATCH 5/5] ASoC: S3C64XX: Fix to support BCLK, LRCLK rates setting Seungwhan Youn
2010-08-06 4:25 ` Jassi Brar
2010-08-06 6:02 ` Seungwhan Youn
2010-08-06 11:17 ` Mark Brown
2010-08-06 16:26 ` Seungwhan Youn
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