* [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270
@ 2010-08-26 10:55 Mikhail Kshevetskiy
2010-08-26 10:55 ` [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 Mikhail Kshevetskiy
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Mikhail Kshevetskiy @ 2010-08-26 10:55 UTC (permalink / raw)
To: u-boot
This board have only one CFI flash actually, so fix it in config.
PS: This patch should not go upstream at this point as it specific
to my revision of voipac
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
---
include/configs/vpac270.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index ddb3e0e..c92eb40 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -192,8 +192,8 @@
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 2010-08-26 10:55 [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Mikhail Kshevetskiy @ 2010-08-26 10:55 ` Mikhail Kshevetskiy 2010-08-26 11:50 ` Marek Vasut 2010-08-26 10:55 ` [U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2 Mikhail Kshevetskiy 2010-08-26 11:50 ` [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Marek Vasut 2 siblings, 1 reply; 6+ messages in thread From: Mikhail Kshevetskiy @ 2010-08-26 10:55 UTC (permalink / raw) To: u-boot The board have only 128 Mb of memory and only two first memory banks are used. Also remove unneeded CONFIG_SYS_DRAM_SIZE constant and set default load address to be in sdram. PS: This patch should not go upstream at this point as it specific to my revision of voipac Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> --- include/configs/vpac270.h | 17 ++++++++++------- 1 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index c92eb40..b04d1e8 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -166,19 +166,22 @@ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_NR_DRAM_BANKS 4 /* We have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_LOAD_ADDR 0xa0000000 /* * NOR FLASH -- 1.7.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 2010-08-26 10:55 ` [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 Mikhail Kshevetskiy @ 2010-08-26 11:50 ` Marek Vasut 0 siblings, 0 replies; 6+ messages in thread From: Marek Vasut @ 2010-08-26 11:50 UTC (permalink / raw) To: u-boot Dne ?t 26. srpna 2010 12:55:45 Mikhail Kshevetskiy napsal(a): > The board have only 128 Mb of memory and only two first memory banks are > used. Also remove unneeded CONFIG_SYS_DRAM_SIZE constant and set default > load address to be in sdram. > > PS: This patch should not go upstream at this point as it specific > to my revision of voipac See my comment on previous patch. Does it work for you? > > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> > --- > include/configs/vpac270.h | 17 ++++++++++------- > 1 files changed, 10 insertions(+), 7 deletions(-) > > diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h > index c92eb40..b04d1e8 100644 > --- a/include/configs/vpac270.h > +++ b/include/configs/vpac270.h > @@ -166,19 +166,22 @@ > /* > * DRAM Map > */ > -#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ > -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ > -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ > -#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ > -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ > +#define CONFIG_NR_DRAM_BANKS 4 /* We have 2 banks of DRAM */ > +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ > +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ > +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ > +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ > +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ > +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ > +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ > +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ > > #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ > -#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ > > #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ > #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ > > -#define CONFIG_SYS_LOAD_ADDR (0x5c000000) > +#define CONFIG_SYS_LOAD_ADDR 0xa0000000 > > /* > * NOR FLASH ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2 2010-08-26 10:55 [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Mikhail Kshevetskiy 2010-08-26 10:55 ` [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 Mikhail Kshevetskiy @ 2010-08-26 10:55 ` Mikhail Kshevetskiy 2010-08-26 12:18 ` Marek Vasut 2010-08-26 11:50 ` [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Marek Vasut 2 siblings, 1 reply; 6+ messages in thread From: Mikhail Kshevetskiy @ 2010-08-26 10:55 UTC (permalink / raw) To: u-boot WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. v1: * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. v2: * rename pxa_mem_setup macro to pxa2xx_mem_setup * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional * skip certain configuration steps if SDRAM is not present/configured * improve/fix comments PS: This patch should not go upstream at this point as it require more work. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> --- arch/arm/include/asm/arch-pxa/macro.h | 78 +++++++++++++++++++++----------- board/vpac270/lowlevel_init.S | 2 +- 2 files changed, 52 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 035a57e..468482a 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,11 +102,15 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_dev_man.pdf */ -.macro pxa_mem_setup +.macro pxa2xx_mem_setup /* This comes handy when setting MDREFR */ ldr r3, =MEMC_BASE + ldr r7, =CONFIG_SYS_MDREFR_VAL /* * 1) Initialize Asynchronous static memory controller @@ -149,51 +153,66 @@ */ /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. + * Before accessing MDREFR we need a valid DRI field. + * Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. + * Optionaly we can set MDREFR[KxFREE] bits. + * So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) + * fields from the config. + * + * WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits + * are usually unset. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN + + /* enable them later, if SDRAM is present */ + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. + /* Initialize SXCNFG register to enable synchronous flash memory. + * While the synchronous flash banks are being configured, the SDRAM + * banks must be disabled and MDREFR[APD] must be de-asserted. */ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* - * 6) Initialize SDRAM + * 6) Initialize SDRAM, + * If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K2RUN] bits + * must be set. Also we must properly configure MDREFR[K1DB2] and + * MDREFR[K2DB2] in this case. + * + * WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present */ + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r6, [r3, #MDREFR_OFFSET] + orr r6, r6, r4 + str r6, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] + bic r6, #MDREFR_SLFRSH str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] orr r6, #MDREFR_E1PIN str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] /* * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure @@ -226,7 +245,7 @@ .endr /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + * 9) Set custom MDCNFG[DEx] bits to enable required SDRAM partitions */ ldr r5, =CONFIG_SYS_MDCNFG_VAL @@ -238,7 +257,10 @@ ldr r4, [r3, #MDCNFG_OFFSET] /* - * 10) Write MDMRS. + * 10) Write to MDMRS register to trigger an MRS command to + * all enabled banks of SDRAM. For each SDRAM partition pair + * that has one or both partitions enabled, this forces a pass + * through the MRS state and a return to NOP. */ ldr r4, =CONFIG_SYS_MDMRS_VAL @@ -246,11 +268,13 @@ ldr r4, [r3, #MDMRS_OFFSET] /* - * 11) Enable APD + * 11) Optionaly enable auto-power-down by setting MDREFR[APD] + * + * WARNING: APD bit is usually set. */ ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD + and r6, r7, #MDREFR_APD orr r4, r4, r6 str r4, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S index ec0d12c..a327ebd 100644 --- a/board/vpac270/lowlevel_init.S +++ b/board/vpac270/lowlevel_init.S @@ -32,7 +32,7 @@ lowlevel_init: pxa_gpio_setup pxa_wait_ticks 0x8000 - pxa_mem_setup + pxa2xx_mem_setup pxa_wakeup pxa_intr_setup pxa_clock_setup -- 1.7.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2 2010-08-26 10:55 ` [U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2 Mikhail Kshevetskiy @ 2010-08-26 12:18 ` Marek Vasut 0 siblings, 0 replies; 6+ messages in thread From: Marek Vasut @ 2010-08-26 12:18 UTC (permalink / raw) To: u-boot Dne ?t 26. srpna 2010 12:55:46 Mikhail Kshevetskiy napsal(a): > WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, > K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was > done early on many pxa platforms. All pxa developers that plan > to use this macro should check the validity of their MDREFR > values. That's a given they should supply correct value, really ... Eric, Haojian, can one of you please look into this? The original file's here: http://git.denx.de/?p=u-boot/u-boot-pxa.git;a=blob;f=arch/arm/include/asm/arch- pxa/macro.h;h=035a57e0af10696b202b6cfc75fd2c6e1e47c83e;hb=refs/heads/for-wd- master Thanks > > v1: > * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. > * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. > > v2: > * rename pxa_mem_setup macro to pxa2xx_mem_setup > * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional > * skip certain configuration steps if SDRAM is not present/configured > * improve/fix comments > > PS: This patch should not go upstream at this point as it require more > work. > > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> > --- > arch/arm/include/asm/arch-pxa/macro.h | 78 > +++++++++++++++++++++----------- board/vpac270/lowlevel_init.S | > 2 +- > 2 files changed, 52 insertions(+), 28 deletions(-) > > diff --git a/arch/arm/include/asm/arch-pxa/macro.h > b/arch/arm/include/asm/arch-pxa/macro.h index 035a57e..468482a 100644 > --- a/arch/arm/include/asm/arch-pxa/macro.h > +++ b/arch/arm/include/asm/arch-pxa/macro.h > @@ -102,11 +102,15 @@ > /* > * This macro sets up the Memory controller of the PXA2xx CPU > * > - * Clobbered regs: r3, r4, r5 > + * Clobbered regs: r3, r4, r5, r6, r7 > + * > + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual > + * > http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x This might change as I know Marvell webdudes ... > _dev_man.pdf */ > -.macro pxa_mem_setup > +.macro pxa2xx_mem_setup Please avoid renaming the macro, you're gonna break other platforms > /* This comes handy when setting MDREFR */ > ldr r3, =MEMC_BASE > + ldr r7, =CONFIG_SYS_MDREFR_VAL Just push this below ... > > /* > * 1) Initialize Asynchronous static memory controller > @@ -149,51 +153,66 @@ > */ > > /* > - * Before accessing MDREFR we need a valid DRI field, so we set > - * this to power on defaults + DRI field. > + * Before accessing MDREFR we need a valid DRI field. > + * Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. > + * Optionaly we can set MDREFR[KxFREE] bits. > + * So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) > + * fields from the config. > + * > + * WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits > + * are usually unset. > */ > ldr r5, [r3, #MDREFR_OFFSET] > - bic r5, r5, #0x0ff > - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ > - > - ldr r4, =CONFIG_SYS_MDREFR_VAL > - mov r6, r4 > - lsl r4, #20 > - lsr r4, #20 /* Get a valid DRI field */ > - > - orr r5, r5, r4 /* MDREFR user config with correct DRI */ > + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ > + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) > + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ > + and r4, r7, r4 > + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ Won't this cause trouble on pxa25x and 26x? Really, that's why I'd rather assume the user isn't moron and will supply the correct MDREFR value. > > orr r5, #MDREFR_K0RUN > orr r5, #MDREFR_SLFRSH > bic r5, #MDREFR_APD > - bic r5, #MDREFR_E1PIN > + > + /* enable them later, if SDRAM is present */ > + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ > + MDREFR_K1DB2 | MDREFR_K2DB2 ) > > str r5, [r3, #MDREFR_OFFSET] > - ldr r4, [r3, #MDREFR_OFFSET] > + ldr r5, [r3, #MDREFR_OFFSET] > > /* > * 5) Initialize Synchronous Static Memory (Flash/Peripherals) > */ > > - /* Initialize SXCNFG register. Assert the enable bits. > - * > - * Write SXMRS to cause an MRS command to all enabled banks of > - * synchronous static memory. Note that SXLCR need not be written > - * at this time. > + /* Initialize SXCNFG register to enable synchronous flash memory. > + * While the synchronous flash banks are being configured, the SDRAM > + * banks must be disabled and MDREFR[APD] must be de-asserted. > */ > write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL > > /* > - * 6) Initialize SDRAM > + * 6) Initialize SDRAM, > + * If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K2RUN] bits > + * must be set. Also we must properly configure MDREFR[K1DB2] and > + * MDREFR[K2DB2] in this case. > + * > + * WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present > */ > > + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ > + MDREFR_K1DB2 | MDREFR_K2DB2 ) > + ldr r6, [r3, #MDREFR_OFFSET] > + orr r6, r6, r4 > + str r6, [r3, #MDREFR_OFFSET] > + ldr r6, [r3, #MDREFR_OFFSET] > + > bic r6, #MDREFR_SLFRSH > str r6, [r3, #MDREFR_OFFSET] > - ldr r4, [r3, #MDREFR_OFFSET] > + ldr r6, [r3, #MDREFR_OFFSET] Shall we use the uservalue here or depend on the readback ? > > orr r6, #MDREFR_E1PIN > str r6, [r3, #MDREFR_OFFSET] > - ldr r4, [r3, #MDREFR_OFFSET] > + ldr r6, [r3, #MDREFR_OFFSET] > Dtto > /* > * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure > @@ -226,7 +245,7 @@ > .endr > > /* > - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). > + * 9) Set custom MDCNFG[DEx] bits to enable required SDRAM partitions > */ > > ldr r5, =CONFIG_SYS_MDCNFG_VAL > @@ -238,7 +257,10 @@ > ldr r4, [r3, #MDCNFG_OFFSET] > > /* > - * 10) Write MDMRS. > + * 10) Write to MDMRS register to trigger an MRS command to > + * all enabled banks of SDRAM. For each SDRAM partition pair > + * that has one or both partitions enabled, this forces a pass > + * through the MRS state and a return to NOP. > */ > > ldr r4, =CONFIG_SYS_MDMRS_VAL > @@ -246,11 +268,13 @@ > ldr r4, [r3, #MDMRS_OFFSET] > > /* > - * 11) Enable APD > + * 11) Optionaly enable auto-power-down by setting MDREFR[APD] > + * > + * WARNING: APD bit is usually set. > */ > > ldr r4, [r3, #MDREFR_OFFSET] > - and r6, r6, #MDREFR_APD > + and r6, r7, #MDREFR_APD Good catch, please send this in a separate patch > orr r4, r4, r6 > str r4, [r3, #MDREFR_OFFSET] > ldr r4, [r3, #MDREFR_OFFSET] > diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S > index ec0d12c..a327ebd 100644 > --- a/board/vpac270/lowlevel_init.S > +++ b/board/vpac270/lowlevel_init.S > @@ -32,7 +32,7 @@ > lowlevel_init: > pxa_gpio_setup > pxa_wait_ticks 0x8000 > - pxa_mem_setup > + pxa2xx_mem_setup > pxa_wakeup > pxa_intr_setup > pxa_clock_setup ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 2010-08-26 10:55 [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Mikhail Kshevetskiy 2010-08-26 10:55 ` [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 Mikhail Kshevetskiy 2010-08-26 10:55 ` [U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2 Mikhail Kshevetskiy @ 2010-08-26 11:50 ` Marek Vasut 2 siblings, 0 replies; 6+ messages in thread From: Marek Vasut @ 2010-08-26 11:50 UTC (permalink / raw) To: u-boot Dne ?t 26. srpna 2010 12:55:44 Mikhail Kshevetskiy napsal(a): > This board have only one CFI flash actually, so fix it in config. > > PS: This patch should not go upstream at this point as it specific > to my revision of voipac > This is a PRO module, right? I got my hands on one and support for it is in for- wd-master ... make vpac270_nor_128M_config . > Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> > --- > include/configs/vpac270.h | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h > index ddb3e0e..c92eb40 100644 > --- a/include/configs/vpac270.h > +++ b/include/configs/vpac270.h > @@ -192,8 +192,8 @@ > #define CONFIG_FLASH_CFI_DRIVER 1 > > #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) > -#define CONFIG_SYS_MAX_FLASH_BANKS 2 > -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } > +#define CONFIG_SYS_MAX_FLASH_BANKS 1 > +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } > > #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) > #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-08-26 12:18 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-08-26 10:55 [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Mikhail Kshevetskiy 2010-08-26 10:55 ` [U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270 Mikhail Kshevetskiy 2010-08-26 11:50 ` Marek Vasut 2010-08-26 10:55 ` [U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2 Mikhail Kshevetskiy 2010-08-26 12:18 ` Marek Vasut 2010-08-26 11:50 ` [U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270 Marek Vasut
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