[PATCH 01/10] imx/clocksource: enable GPT1 before using it on CPUIMX25

[PATCH 01/10] imx/clocksource: enable GPT1 before using it on CPUIMX25

[Eric Bénard]

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/mach-imx/clocksource.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index a166038..b3a74b3 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -76,6 +76,10 @@ static int clocksource_init (void)
 	PCCR0 |= PCCR0_GPT1_EN;
 	PCCR1 |= PCCR1_PERCLK1_EN;
 #endif
+#ifdef CONFIG_ARCH_IMX25
+	writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19),
+		IMX_CCM_BASE + CCM_CGCR1);
+#endif
 
 	for (i = 0; i < 100; i++)
 		writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
-- 
1.7.0.4


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[PATCH 02/10] mx25: add MMC clock support

[Eric Bénard]

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/mach-imx/speed-imx25.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c
index 9605674..e8feb6b 100644
--- a/arch/arm/mach-imx/speed-imx25.c
+++ b/arch/arm/mach-imx/speed-imx25.c
@@ -82,6 +82,11 @@ unsigned long imx_get_i2cclk(void)
 	return imx_get_perclk(6);
 }
 
+unsigned long imx_get_mmcclk(void)
+{
+	return imx_get_perclk(3);
+}
+
 int imx_dump_clocks(void)
 {
 	printf("mpll:    %10d Hz\n", imx_get_mpllclk());
@@ -92,6 +97,8 @@ int imx_dump_clocks(void)
 	printf("gpt:     %10d Hz\n", imx_get_ipgclk());
 	printf("nand:    %10d Hz\n", imx_get_perclk(8));
 	printf("lcd:     %10d Hz\n", imx_get_perclk(7));
+	printf("i2c:     %10d Hz\n", imx_get_perclk(6));
+	printf("sdhc1:   %10d Hz\n", imx_get_perclk(3));
 	return 0;
 }
 
-- 
1.7.0.4


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[PATCH 03/10] MX25: fix IOMUX for ESDHC1 pins

[Eric Bénard]

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/mach-imx/include/mach/iomux-mx25.h |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h
index a290a33..a8ca8f1 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx25.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx25.h
@@ -658,21 +658,21 @@
 #define MX25_PAD_RW__EIM_RW                                IOMUX_PAD(0x278,  0x6c, 0,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_RW__AUD4_TXFS                             IOMUX_PAD(0x278,  0x6c, 4, 0x474, 0, NO_PAD_CTRL)
 #define MX25_PAD_RW__GPIO25                                IOMUX_PAD(0x278,  0x6c, 5,     0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__CLK                              IOMUX_PAD(0x38c, 0x194, 0,     0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_CLK__CLK                              IOMUX_PAD(0x38c, 0x194, 0x10,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__MISO                             IOMUX_PAD(0x38c, 0x194, 1, 0x49c, 1, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__RDATA3                           IOMUX_PAD(0x38c, 0x194, 2, 0x510, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__SDMA_DBG_STAT_0                  IOMUX_PAD(0x38c, 0x194, 4,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__GPIO24                           IOMUX_PAD(0x38c, 0x194, 5,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__SLCDC_DATA1                      IOMUX_PAD(0x38c, 0x194, 6,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CLK__TRACE11                          IOMUX_PAD(0x38c, 0x194, 7,     0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__CMD                              IOMUX_PAD(0x388, 0x190, 0,     0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_CMD__CMD                              IOMUX_PAD(0x388, 0x190, 0x10,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__MOSI                             IOMUX_PAD(0x388, 0x190, 1, 0x4a0, 1, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__RDATA2                           IOMUX_PAD(0x388, 0x190, 2, 0x50c, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__SDMA_DBG_EVT_SEL                 IOMUX_PAD(0x388, 0x190, 4,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__GPIO23                           IOMUX_PAD(0x388, 0x190, 5,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__SLCDC_DATA0                      IOMUX_PAD(0x388, 0x190, 6,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_CMD__TRACE10                          IOMUX_PAD(0x388, 0x190, 7,     0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA0__DAT0                           IOMUX_PAD(0x390, 0x198, 0,     0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA0__DAT0                           IOMUX_PAD(0x390, 0x198, 0x10,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA0__SCLK                           IOMUX_PAD(0x390, 0x198, 1, 0x494, 1, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA0__TDATA2                         IOMUX_PAD(0x390, 0x198, 2,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA0__AUD7_TXFS                      IOMUX_PAD(0x390, 0x198, 3, 0x47c, 0, NO_PAD_CTRL)
@@ -680,7 +680,7 @@
 #define MX25_PAD_SD1_DATA0__GPIO25                         IOMUX_PAD(0x390, 0x198, 5,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA0__SLCDC_DATA2                    IOMUX_PAD(0x390, 0x198, 6,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA0__TRACE12                        IOMUX_PAD(0x390, 0x198, 7,     0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__DAT1                           IOMUX_PAD(0x394, 0x19c, 0,     0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA1__DAT1                           IOMUX_PAD(0x394, 0x19c, 0x10,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA1__RDY                            IOMUX_PAD(0x394, 0x19c, 1, 0x498, 1, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA1__TDATA3                         IOMUX_PAD(0x394, 0x19c, 2,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA1__AUD7_RXD                       IOMUX_PAD(0x394, 0x19c, 3, 0x478, 0, NO_PAD_CTRL)
@@ -688,7 +688,7 @@
 #define MX25_PAD_SD1_DATA1__GPIO26                         IOMUX_PAD(0x394, 0x19c, 5,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA1__SLCDC_DATA3                    IOMUX_PAD(0x394, 0x19c, 6,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA1__TRACE13                        IOMUX_PAD(0x394, 0x19c, 7,     0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__DAT2                           IOMUX_PAD(0x398, 0x1a0, 0,     0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA2__DAT2                           IOMUX_PAD(0x398, 0x1a0, 0x10,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__SS0                            IOMUX_PAD(0x398, 0x1a0, 1, 0x4a4, 1, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__RX_CLK                         IOMUX_PAD(0x398, 0x1a0, 2, 0x514, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__AUD7_RXC                       IOMUX_PAD(0x398, 0x1a0, 3,     0, 0, NO_PAD_CTRL)
@@ -696,7 +696,7 @@
 #define MX25_PAD_SD1_DATA2__GPIO27                         IOMUX_PAD(0x398, 0x1a0, 5,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__SLCDC_DATA4                    IOMUX_PAD(0x398, 0x1a0, 6,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA2__TRACE14                        IOMUX_PAD(0x398, 0x1a0, 7,     0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__DAT3                           IOMUX_PAD(0x39c, 0x1a4, 0,     0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA3__DAT3                           IOMUX_PAD(0x39c, 0x1a4, 0x10,     0, 0, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__SS1                            IOMUX_PAD(0x39c, 0x1a4, 1, 0x4a8, 1, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__CRS                            IOMUX_PAD(0x39c, 0x1a4, 2, 0x508, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__AUD7_RXFS                      IOMUX_PAD(0x39c, 0x1a4, 3,     0, 0, NO_PAD_CTRL)
-- 
1.7.0.4


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[PATCH 04/10] mci-core: add more tested SD Cards

[Eric Bénard]

note :
- Transcend 16GiB fails (no log)
- Micron 8GiB eMMC fails (hangs after : Detecting a 4.0 revision card)

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 drivers/mci/mci-core.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index ea27062..c92d5a9 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -46,9 +46,12 @@
  *
  * Checked with the following cards:
  * - Canon MMC 16 MiB
+ * - Integral MicroSDHC, 8 GiB (Class 4)
  * - Kingston 512 MiB
  * - SanDisk 512 MiB
  * - Transcend SD Ultra, 1 GiB (Industrial)
+ * - Transcend SDHC, 4 GiB (Class 6)
+ * - Transcend SDHC, 8 GiB (Class 6)
  */
 
 /**
-- 
1.7.0.4


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[PATCH 05/10] epautoconf: fix compile error

[Eric Bénard]

this patch fix the following error :
  CC      drivers/usb/gadget/epautoconf.o
drivers/usb/gadget/epautoconf.c:33: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'unsigned'
drivers/usb/gadget/epautoconf.c: In function 'ep_matches':
drivers/usb/gadget/epautoconf.c:168: error: 'epnum' undeclared (first use in this function)
drivers/usb/gadget/epautoconf.c:168: error: (Each undeclared identifier is reported only once
drivers/usb/gadget/epautoconf.c:168: error: for each function it appears in.)
drivers/usb/gadget/epautoconf.c: In function 'usb_ep_autoconfig_reset':
drivers/usb/gadget/epautoconf.c:304: error: 'epnum' undeclared (first use in this function)

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 drivers/usb/gadget/epautoconf.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index e549792..fe7e7fd 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -19,6 +19,7 @@
  *
  */
 
+#include <init.h>
 #include <common.h>
 #include <linux/ctype.h>
 #include <asm/byteorder.h>
-- 
1.7.0.4


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[PATCH 06/10] eukrea_cpuimx25: update board support

[Eric Bénard]

- support NAND external boot
- enable only used clocks
- LCD fix in /env/bin/init
- I2C support
- SDCard support
- USB Host 1 support
- DFU support on OTG port
- update defconfig

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/boards/eukrea_cpuimx25/env/bin/init      |    2 +
 arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c |  104 +++++++++++++++++++-
 arch/arm/boards/eukrea_cpuimx25/lowlevel.c        |   64 ++++++++++---
 arch/arm/configs/eukrea_cpuimx25_defconfig        |   12 ++-
 4 files changed, 162 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/init b/arch/arm/boards/eukrea_cpuimx25/env/bin/init
index 335d7ae..4732875 100644
--- a/arch/arm/boards/eukrea_cpuimx25/env/bin/init
+++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/init
@@ -14,9 +14,11 @@ fi
 
 if [ -f /env/logo.bmp ]; then
 	bmp /env/logo.bmp
+	fb0.enable=1
 elif [ -f /env/logo.bmp.lzo ]; then
 	unlzo /env/logo.bmp.lzo /logo.bmp
 	bmp /logo.bmp
+	fb0.enable=1
 fi
 
 if [ -z $eth0.ethaddr ]; then
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 7fd1031..c2eb398 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -40,6 +40,8 @@
 #include <nand.h>
 #include <mach/imx-flash-header.h>
 #include <mach/iomux-mx25.h>
+#include <i2c/i2c.h>
+#include <usb/fsl_usb2.h>
 
 extern unsigned long _stext;
 extern void exception_vectors(void);
@@ -151,6 +153,70 @@ static struct device_d imxfb_dev = {
 	.platform_data	= &eukrea_cpuimx25_fb_data,
 };
 
+static struct device_d i2c_dev = {
+	.id	  = -1,
+	.name     = "i2c-imx",
+	.map_base = IMX_I2C1_BASE,
+};
+
+static struct device_d esdhc_dev = {
+	.name		= "imx-esdhc",
+	.map_base	= 0x53fb4000,
+};
+
+#ifdef CONFIG_USB
+
+#define MX35_H1_SIC_SHIFT	21
+#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT		(1 << 8)
+#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX35_H1_TLL_BIT		(1 << 5)
+#define MX35_H1_USBTE_BIT	(1 << 4)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+
+static void imx25_usb_init(void)
+{
+	unsigned int tmp;
+
+	/* Host 1 */
+	tmp = readl(IMX_OTG_BASE + 0x600);
+	tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+		MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+	tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
+	tmp |= MX35_H1_USBTE_BIT;
+	tmp |= MX35_H1_IPPUE_DOWN_BIT;
+	writel(tmp, IMX_OTG_BASE + 0x600);
+
+	tmp = readl(IMX_OTG_BASE + 0x584);
+	tmp |= 3 << 30;
+	writel(tmp, IMX_OTG_BASE + 0x584);
+
+	/* Set to Host mode */
+	tmp = readl(IMX_OTG_BASE + 0x5a8);
+	writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+}
+
+static struct device_d usbh2_dev = {
+	.id	  = -1,
+	.name     = "ehci",
+	.map_base = IMX_OTG_BASE + 0x400,
+	.size     = 0x200,
+};
+#endif
+
+static struct fsl_usb2_platform_data usb_pdata = {
+	.operating_mode	= FSL_USB2_DR_DEVICE,
+	.phy_mode	= FSL_USB2_PHY_UTMI,
+};
+
+static struct device_d usbotg_dev = {
+	.name     = "fsl-udc",
+	.map_base = IMX_OTG_BASE,
+	.size     = 0x200,
+	.platform_data = &usb_pdata,
+};
+
 #ifdef CONFIG_MMU
 static void eukrea_cpuimx25_mmu_init(void)
 {
@@ -209,6 +275,16 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
 	MX25_PAD_HSYNC__LCDC_HSYN,
 	/* BACKLIGHT CONTROL */
 	MX25_PAD_PWM__GPIO26,
+	/* I2C */
+	MX25_PAD_I2C1_CLK__SCL,
+	MX25_PAD_I2C1_DAT__SDA,
+	/* SDCard */
+	MX25_PAD_SD1_CLK__CLK,
+	MX25_PAD_SD1_CMD__CMD,
+	MX25_PAD_SD1_DATA0__DAT0,
+	MX25_PAD_SD1_DATA1__DAT1,
+	MX25_PAD_SD1_DATA2__DAT2,
+	MX25_PAD_SD1_DATA3__DAT3,
 };
 
 static int eukrea_cpuimx25_devices_init(void)
@@ -217,6 +293,7 @@ static int eukrea_cpuimx25_devices_init(void)
 
 	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
 		ARRAY_SIZE(eukrea_cpuimx25_pads));
+
 	register_device(&fec_dev);
 
 	nand_info.width = 1;
@@ -238,6 +315,15 @@ static int eukrea_cpuimx25_devices_init(void)
 
 	register_device(&imxfb_dev);
 
+	register_device(&i2c_dev);
+	register_device(&esdhc_dev);
+
+#ifdef CONFIG_USB
+	imx25_usb_init();
+	register_device(&usbh2_dev);
+#endif
+	register_device(&usbotg_dev);
+
 	armlinux_add_dram(&sdram0_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25);
@@ -256,7 +342,6 @@ static struct device_d eukrea_cpuimx25_serial_device = {
 
 static int eukrea_cpuimx25_console_init(void)
 {
-	writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3);
 	register_device(&eukrea_cpuimx25_serial_device);
 	return 0;
 }
@@ -270,10 +355,17 @@ void __bare_init nand_boot(void)
 }
 #endif
 
-static int eukrea_cpuimx25_core_setup(void)
-{
-	writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
-	return 0;
+static int eukrea_cpuimx25_core_init(void) {
+	/* enable UART1, FEC, SDHC, USB & I2C clock */
+	writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23)
+		| (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28),
+		IMX_CCM_BASE + CCM_CGCR0);
+	writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15)
+		| (1 << 13), IMX_CCM_BASE + CCM_CGCR1);
+	writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14),
+		IMX_CCM_BASE + CCM_CGCR2);
 
+	return 0;
 }
-core_initcall(eukrea_cpuimx25_core_setup);
+
+core_initcall(eukrea_cpuimx25_core_init);
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index b9d3ce5..4ebf247 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -26,13 +26,13 @@
 #include <mach/imx-regs.h>
 #include <mach/imx-pll.h>
 #include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
 #include <asm/io.h>
 #include <mach/imx-nand.h>
 #include <asm/barebox-arm.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/system.h>
 
+#ifdef CONFIG_NAND_IMX_BOOT
 static void __bare_init __naked insdram(void)
 {
 	uint32_t r;
@@ -45,17 +45,32 @@ static void __bare_init __naked insdram(void)
 
 	board_init_lowlevel_return();
 }
-
-#define MX25_CCM_MCR	0x64
-#define MX25_CCM_CGR0	0x0c
-#define MX25_CCM_CGR1	0x10
-#define MX25_CCM_CGR2	0x14
+#endif
 
 void __bare_init __naked board_init_lowlevel(void)
 {
 	uint32_t r;
+#ifdef CONFIG_NAND_IMX_BOOT
 	unsigned int *trg, *src;
 	int i;
+#endif
+	register uint32_t loops = 0x20000;
+
+	/* restart the MPLL and wait until it's stable */
+	writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),
+						IMX_CCM_BASE + CCM_CCTL);
+	while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};
+
+	/* Configure dividers and ARM clock source
+	 * 	ARM @ 400 MHz
+	 * 	AHB @ 133 MHz
+	 */
+	writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
+
+	/* Enable UART1 / FEC / */
+/*	writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0);
+	writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1);
+	writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/
 
 	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -102,23 +117,46 @@ void __bare_init __naked board_init_lowlevel(void)
 	 */
 	writel(0x1, 0xb8003000);
 
-	/* enable all the clocks */
-	writel(0x038A81A2, IMX_CCM_BASE + MX25_CCM_CGR0);
-	writel(0x24788F00, IMX_CCM_BASE + MX25_CCM_CGR1);
-	writel(0x00004438, IMX_CCM_BASE + MX25_CCM_CGR2);
-	writel(0x00, IMX_CCM_BASE + MX25_CCM_MCR);
+	/* Speed up NAND controller by adjusting the NFC divider */
+	r = readl(IMX_CCM_BASE + CCM_PCDR2);
+	r &= ~0xf;
+	r |= 0x1;
+	writel(r, IMX_CCM_BASE + CCM_PCDR2);
+
+	/* Skip SDRAM initialization if we run from RAM */
+	r = get_pc();
+	if (r > 0x80000000 && r < 0x90000000)
+		board_init_lowlevel_return();
+
+	/* Init Mobile DDR */
+	writel(0x0000000E, ESDMISC);
+	writel(0x00000004, ESDMISC);
+	__asm__ volatile ("1:\n"
+			"subs %0, %1, #1\n"
+			"bne 1b":"=r" (loops):"0" (loops));
+
+	writel(0x0029572B, ESDCFG0);
+	writel(0x92210000, ESDCTL0);
+	writeb(0xda, IMX_SDRAM_CS0 + 0x400);
+	writel(0xA2210000, ESDCTL0);
+	writeb(0xda, IMX_SDRAM_CS0);
+	writeb(0xda, IMX_SDRAM_CS0);
+	writel(0xB2210000, ESDCTL0);
+	writeb(0xda, IMX_SDRAM_CS0 + 0x33);
+	writeb(0xda, IMX_SDRAM_CS0 + 0x1000000);
+	writel(0x82216080, ESDCTL0);
 
 #ifdef CONFIG_NAND_IMX_BOOT
 	/* skip NAND boot if not running from NFC space */
 	r = get_pc();
-	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000)
+	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
 		board_init_lowlevel_return();
 
 	src = (unsigned int *)IMX_NFC_BASE;
 	trg = (unsigned int *)TEXT_BASE;
 
 	/* Move ourselves out of NFC SRAM */
-	for (i = 0; i < 0x1000 / sizeof(int); i++)
+	for (i = 0; i < 0x800 / sizeof(int); i++)
 		*trg++ = *src++;
 
 	/* Jump to SDRAM */
diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig
index feb758e..bc68804 100644
--- a/arch/arm/configs/eukrea_cpuimx25_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx25_defconfig
@@ -9,6 +9,7 @@ CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_PROMPT_HUSH_PS2="cpuimx25>"
 CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_PARTITION=y
@@ -23,6 +24,7 @@ CONFIG_CMD_READLINE=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_BOOTM_ZLIB=y
@@ -35,15 +37,23 @@ CONFIG_CMD_PARTITION=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_UNLZO=y
+CONFIG_CMD_I2C=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
 CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
 CONFIG_DRIVER_NET_FEC_IMX=y
 # CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_GADGET=y
 CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_IMX=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_IMX_ESDHC_PIO=y
-- 
1.7.0.4


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Re: [PATCH 06/10] eukrea_cpuimx25: update board support

[Baruch Siach]

Hi Eric,

On Thu, Oct 14, 2010 at 04:05:28PM +0200, Eric Bénard wrote:
> - support NAND external boot
> - enable only used clocks
> - LCD fix in /env/bin/init
> - I2C support
> - SDCard support
> - USB Host 1 support
> - DFU support on OTG port
> - update defconfig
> 
> Signed-off-by: Eric Bénard <eric@eukrea.com>
> ---
>  arch/arm/boards/eukrea_cpuimx25/env/bin/init      |    2 +
>  arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c |  104 +++++++++++++++++++-
>  arch/arm/boards/eukrea_cpuimx25/lowlevel.c        |   64 ++++++++++---
>  arch/arm/configs/eukrea_cpuimx25_defconfig        |   12 ++-
>  4 files changed, 162 insertions(+), 20 deletions(-)

[snip]

> diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c 
> b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
> index 7fd1031..c2eb398 100644
> --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
> +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c

[snip]

> +#ifdef CONFIG_USB
> +
> +#define MX35_H1_SIC_SHIFT	21
> +#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
> +#define MX35_H1_PM_BIT		(1 << 8)
> +#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
> +#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
> +#define MX35_H1_TLL_BIT		(1 << 5)
> +#define MX35_H1_USBTE_BIT	(1 << 4)
> +#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)

The exact same defines appear in patch no. 10 of this series. IMO these should 
go into a shared header file.

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -

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Re: [PATCH 06/10] eukrea_cpuimx25: update board support

[Eric Bénard]

Hi Baruch,

Le 16/10/2010 21:01, Baruch Siach a écrit :
>> +#ifdef CONFIG_USB
>> +
>> +#define MX35_H1_SIC_SHIFT	21
>> +#define MX35_H1_SIC_MASK	(0x3<<  MX35_H1_SIC_SHIFT)
>> +#define MX35_H1_PM_BIT		(1<<  8)
>> +#define MX35_H1_IPPUE_UP_BIT	(1<<  7)
>> +#define MX35_H1_IPPUE_DOWN_BIT	(1<<  6)
>> +#define MX35_H1_TLL_BIT		(1<<  5)
>> +#define MX35_H1_USBTE_BIT	(1<<  4)
>> +#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2<<  0)
>
> The exact same defines appear in patch no. 10 of this series. IMO these should
> go into a shared header file.
>
done, thanks for the review.

Eric

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[PATCH 07/10] imx35-regs: add defines for USB and SD

[Eric Bénard]

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/mach-imx/include/mach/imx35-regs.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 5cfb788..b2b360a 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -51,6 +51,7 @@
 #define IMX_SDHC1_BASE		0x53FB4000
 #define IMX_SDHC2_BASE		0x53FB8000
 #define IMX_SDHC3_BASE		0x53FBC000
+#define IMX_OTG_BASE		0x53FF4000
 
 /*
  * Clock Controller Module (CCM)
@@ -73,6 +74,8 @@
 
 #define CCM_CGR1_FEC_SHIFT	0
 #define CCM_CGR1_I2C1_SHIFT	10
+#define CCM_CGR1_SDHC1_SHIFT	26
+#define CCM_CGR2_USB_SHIFT	22
 
 #define PDR0_AUTO_MUX_DIV(x)	(((x) & 0x7) << 9)
 #define PDR0_CCM_PER_AHB(x)	(((x) & 0x7) << 12)
-- 
1.7.0.4


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[PATCH 08/10] speed-imx35: add support for SDHC1

[Eric Bénard]

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/mach-imx/speed-imx35.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index c5a31c7..324cc29 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -163,6 +163,17 @@ unsigned long imx_get_uartclk(void)
 		return imx_get_ppllclk() / div;
 }
 
+unsigned long imx_get_mmcclk(void)
+{
+	unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
+	unsigned long div = get_3_3_div(pdr3);
+
+	if (pdr3 & (1 << 6))
+		return imx_get_armclk() / div;
+	else
+		return imx_get_ppllclk() / div;
+}
+
 ulong imx_get_fecclk(void)
 {
 	return imx_get_ipgclk();
@@ -183,6 +194,7 @@ void imx_dump_clocks(void)
 	printf("ipg:     %10d Hz\n", imx_get_ipgclk());
 	printf("ipg_per: %10d Hz\n", imx_get_ipg_perclk());
 	printf("uart:	 %10d Hz\n", imx_get_uartclk());
+	printf("sdhc1:   %10d Hz\n", imx_get_mmcclk());
 }
 
 /*
-- 
1.7.0.4


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[PATCH 09/10] iomux-mx35: fox IOMUX for SDHC1's pins

[Eric Bénard]

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/mach-imx/include/mach/iomux-mx35.h |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h
index 8a56d86..ad7ff56 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx35.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx35.h
@@ -815,42 +815,42 @@
 #define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1		IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22			IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_SD1_CMD__ESDHC1_CMD				IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__ESDHC1_CMD				IOMUX_PAD(0x694, 0x230, 0x10, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CMD__MSHC_SCLK				IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC			IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4			IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CMD__GPIO1_6				IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL			IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_SD1_CLK__ESDHC1_CLK				IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__ESDHC1_CLK				IOMUX_PAD(0x698, 0x234, 0x10, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CLK__MSHC_BS				IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK			IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5			IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CLK__GPIO1_7				IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL)
 #define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK			IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0				IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0				IOMUX_PAD(0x69c, 0x238, 0x10, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA0__MSHC_DATA_0				IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0			IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6		IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA0__GPIO1_8				IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23			IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1				IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1				IOMUX_PAD(0x6a0, 0x23c, 0x10, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA1__MSHC_DATA_1				IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS			IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0		IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA1__GPIO1_9				IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24			IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2				IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2				IOMUX_PAD(0x6a4, 0x240, 0x10, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA2__MSHC_DATA_2				IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA2__IPU_DISPB_WR			IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1		IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA2__GPIO1_10				IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25			IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL)
 
-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3				IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3				IOMUX_PAD(0x6a8, 0x244, 0x10, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA3__MSHC_DATA_3				IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA3__IPU_DISPB_RD			IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2		IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL)
-- 
1.7.0.4


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[PATCH 10/10] eukrea_cpuimx35: update board support

[Eric Bénard]

- support NAND external boot
- update internal boot init sequence
- unbreak flash_header using magic values ...
- LCD enable
- add I2C
- add SDCard
- add USB Host
- add DFU on USB OTG

Signed-off-by: Eric Bénard <eric@eukrea.com>
---
 arch/arm/boards/eukrea_cpuimx35/env/bin/init      |    4 +-
 arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c |   99 ++++++++++++++++++++-
 arch/arm/boards/eukrea_cpuimx35/flash_header.c    |   22 +++---
 arch/arm/boards/eukrea_cpuimx35/lowlevel.c        |   20 +++--
 arch/arm/configs/eukrea_cpuimx35_defconfig        |   14 +++-
 5 files changed, 135 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/init b/arch/arm/boards/eukrea_cpuimx35/env/bin/init
index 90007cd..b56d7b5 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/bin/init
+++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/init
@@ -15,12 +15,12 @@ fi
 if [ -f /env/logo.bmp ]; then
 	fb0.enable=1
 	bmp /env/logo.bmp
-	gpio_direction_out 1 1
+	gpio_set_value 1 1
 elif [ -f /env/logo.bmp.lzo ]; then
 	unlzo /env/logo.bmp.lzo /logo.bmp
 	fb0.enable=1
 	bmp /logo.bmp
-	gpio_direction_out 1 1
+	gpio_set_value 1 1
 fi
 
 if [ -z $eth0.ethaddr ]; then
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 63d019a..7d85f97 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -51,6 +51,8 @@
 #include <mach/pmic.h>
 #include <mach/imx-ipu-fb.h>
 #include <mach/imx-pll.h>
+#include <i2c/i2c.h>
+#include <usb/fsl_usb2.h>
 
 static struct fec_platform_data fec_info = {
 	.xcv_type	= MII100,
@@ -126,6 +128,70 @@ static struct device_d imxfb_dev = {
 	.platform_data	= &ipu_fb_data,
 };
 
+static struct device_d i2c_dev = {
+	.id	  = -1,
+	.name     = "i2c-imx",
+	.map_base = IMX_I2C1_BASE,
+};
+
+static struct device_d esdhc_dev = {
+	.name		= "imx-esdhc",
+	.map_base	= IMX_SDHC1_BASE,
+};
+
+#ifdef CONFIG_USB
+
+#define MX35_H1_SIC_SHIFT	21
+#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT		(1 << 8)
+#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
+#define MX35_H1_TLL_BIT		(1 << 5)
+#define MX35_H1_USBTE_BIT	(1 << 4)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+
+static void imx35_usb_init(void)
+{
+	unsigned int tmp;
+
+	/* Host 1 */
+	tmp = readl(IMX_OTG_BASE + 0x600);
+	tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+		MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+	tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
+	tmp |= MX35_H1_USBTE_BIT;
+	tmp |= MX35_H1_IPPUE_DOWN_BIT;
+	writel(tmp, IMX_OTG_BASE + 0x600);
+
+	tmp = readl(IMX_OTG_BASE + 0x584);
+	tmp |= 3 << 30;
+	writel(tmp, IMX_OTG_BASE + 0x584);
+
+	/* Set to Host mode */
+	tmp = readl(IMX_OTG_BASE + 0x5a8);
+	writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+}
+
+static struct device_d usbh2_dev = {
+	.id	  = -1,
+	.name     = "ehci",
+	.map_base = IMX_OTG_BASE + 0x400,
+	.size     = 0x200,
+};
+#endif
+
+static struct fsl_usb2_platform_data usb_pdata = {
+	.operating_mode	= FSL_USB2_DR_DEVICE,
+	.phy_mode	= FSL_USB2_PHY_UTMI,
+};
+
+static struct device_d usbotg_dev = {
+	.name     = "fsl-udc",
+	.map_base = IMX_OTG_BASE,
+	.size     = 0x200,
+	.platform_data = &usb_pdata,
+};
+
 #ifdef CONFIG_MMU
 static int eukrea_cpuimx35_mmu_init(void)
 {
@@ -153,6 +219,8 @@ postcore_initcall(eukrea_cpuimx35_mmu_init);
 
 static int eukrea_cpuimx35_devices_init(void)
 {
+	unsigned int tmp;
+
 	register_device(&nand_dev);
 
 	devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
@@ -165,6 +233,18 @@ static int eukrea_cpuimx35_devices_init(void)
 	register_device(&sdram_dev);
 	register_device(&imxfb_dev);
 
+	register_device(&i2c_dev);
+	register_device(&esdhc_dev);
+
+#ifdef CONFIG_USB
+	imx35_usb_init();
+	register_device(&usbh2_dev);
+#endif
+	/* Workaround ENGcm09152 */
+	tmp = readl(IMX_OTG_BASE + 0x608);
+	writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
+	register_device(&usbotg_dev);
+
 	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
@@ -211,6 +291,16 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
 	MX35_PAD_LD23__GPIO3_29,
 	MX35_PAD_CONTRAST__GPIO1_1,
 	MX35_PAD_D3_CLS__GPIO1_4,
+
+	MX35_PAD_I2C1_CLK__I2C1_SCL,
+	MX35_PAD_I2C1_DAT__I2C1_SDA,
+
+	MX35_PAD_SD1_CMD__ESDHC1_CMD,
+	MX35_PAD_SD1_CLK__ESDHC1_CLK,
+	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
 static int eukrea_cpuimx35_console_init(void)
@@ -219,7 +309,7 @@ static int eukrea_cpuimx35_console_init(void)
 		ARRAY_SIZE(eukrea_cpuimx35_pads));
 
 	/* screen default on to prevent flicker */
-	gpio_direction_output(4, 1);
+	gpio_direction_output(4, 0);
 	/* backlight default off */
 	gpio_direction_output(1, 0);
 	/* led default off */
@@ -235,10 +325,15 @@ static int eukrea_cpuimx35_core_init(void)
 {
 	u32 reg;
 
-	/* enable clock for I2C1 and FEC */
+	/* enable clock for I2C1, SDHC1, USB and FEC */
 	reg = readl(IMX_CCM_BASE + CCM_CGR1);
 	reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
+	reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
+	reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
 	reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
+	reg = readl(IMX_CCM_BASE + CCM_CGR2);
+	reg |= 0x3 << CCM_CGR2_USB_SHIFT;
+	reg = writel(reg, IMX_CCM_BASE + CCM_CGR2);
 
 	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
 	/*
diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
index 285a2d4..4163caf 100644
--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
@@ -12,24 +12,24 @@ void __naked __flash_header_start go(void)
 struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
 	{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
 	{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
-	{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
+	{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
 	{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
-	{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x0009572B, },
-	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
+	{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x0009572B, },
+	{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92220000, },
 	{ .ptr_type = 1, .addr = 0x80000400, .val = 0xda, },
-	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
-	{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
-	{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
-	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
+	{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2220000, },
+	{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
+	{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
+	{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2220000, },
 	{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
 	{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
-	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82224080, },
-	{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
+	{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82224080, },
+	{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
 };
 
-
+#define DEST_BASE 0x80000000
 struct imx_flash_header __flash_header_section flash_header = {
-	.app_code_jump_vector	= DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),
+	.app_code_jump_vector	= DEST_BASE + 0x1000,
 	.app_code_barker	= APP_CODE_BARKER,
 	.app_code_csf		= 0,
 	.dcd_ptr_ptr		= FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index aad334d..6c0e106 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -66,6 +66,7 @@ void __bare_init __naked board_init_lowlevel(void)
 	unsigned int *trg, *src;
 	int i;
 #endif
+	register uint32_t loops = 0x20000;
 
 	r = get_cr();
 	r |= CR_Z; /* Flow prediction (Z) */
@@ -118,7 +119,7 @@ void __bare_init __naked board_init_lowlevel(void)
 	writel(r, ccm_base + CCM_CGR0);
 
 	r = readl(ccm_base + CCM_CGR1);
-	r |= 0x00000C00;
+	r |= 0x00030C00;
 	r |= 0x00000003;
 	writel(r, ccm_base + CCM_CGR1);
 
@@ -132,31 +133,34 @@ void __bare_init __naked board_init_lowlevel(void)
 		board_init_lowlevel_return();
 
 	/* Init Mobile DDR */
+	writel(0x0000000E, ESDMISC);
 	writel(0x00000004, ESDMISC);
-	writel(0x0000000C, ESDMISC);
+	__asm__ volatile ("1:\n"
+			"subs %0, %1, #1\n"
+			"bne 1b":"=r" (loops):"0" (loops));
+
 	writel(0x0009572B, ESDCFG0);
 	writel(0x92220000, ESDCTL0);
 	writeb(0xda, IMX_SDRAM_CS0 + 0x400);
 	writel(0xA2220000, ESDCTL0);
-	writel(0x87654321, IMX_SDRAM_CS0);
-	writel(0x87654321, IMX_SDRAM_CS0);
+	writeb(0xda, IMX_SDRAM_CS0);
+	writeb(0xda, IMX_SDRAM_CS0);
 	writel(0xB2220000, ESDCTL0);
 	writeb(0xda, IMX_SDRAM_CS0 + 0x33);
 	writeb(0xda, IMX_SDRAM_CS0 + 0x2000000);
-	writel(0x82224080, ESDCTL0);
-	writel(0x00000004, ESDMISC);
+	writel(0x82228080, ESDCTL0);
 
 #ifdef CONFIG_NAND_IMX_BOOT
 	/* skip NAND boot if not running from NFC space */
 	r = get_pc();
-	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000)
+	if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
 		board_init_lowlevel_return();
 
 	src = (unsigned int *)IMX_NFC_BASE;
 	trg = (unsigned int *)TEXT_BASE;
 
 	/* Move ourselves out of NFC SRAM */
-	for (i = 0; i < 0x1000 / sizeof(int); i++)
+	for (i = 0; i < 0x800 / sizeof(int); i++)
 		*trg++ = *src++;
 
 	/* Jump to SDRAM */
diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig
index 975d095..af82827 100644
--- a/arch/arm/configs/eukrea_cpuimx35_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx35_defconfig
@@ -8,8 +8,11 @@ CONFIG_MALLOC_SIZE=0x800000
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
+# CONFIG_CONSOLE_ACTIVATE_FIRST is not set
+CONFIG_CONSOLE_ACTIVATE_ALL=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx35/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
@@ -22,6 +25,7 @@ CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_RESET=y
@@ -31,15 +35,23 @@ CONFIG_CMD_PARTITION=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_UNLZO=y
+CONFIG_CMD_I2C=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
 CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
 CONFIG_DRIVER_NET_FEC_IMX=y
 # CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_GADGET=y
 CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_IMX_IPU=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_IMX_ESDHC_PIO=y
-- 
1.7.0.4


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