From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Andi Kleen <andi@firstfloor.org>,
Corey Ashford <cjashfor@linux.vnet.ibm.com>,
Andi Kleen <ak@linux.intel.com>,
linux-kernel@vger.kernel.org, fweisbec@gmail.com, mingo@elte.hu,
acme@redhat.com
Subject: Re: [PATCH 2/3] perf: Add support for extra parameters for raw events
Date: Fri, 12 Nov 2010 11:48:04 +0100 [thread overview]
Message-ID: <20101112104804.GB8020@basil.fritz.box> (raw)
In-Reply-To: <AANLkTin3khDj2FpJ-SY+xhLykiKer23uAjRdBM4m8gXD@mail.gmail.com>
> I don't think you need special syntax. You can simply come up with
> the 64-bit raw hex value. corey recently added a small utility to do
> this via libpfm4: perf stat -e `evt2raw unhalted_core_cycles:u` ....
I added a small patch to perf to read event mappings from a flat mapping file.
> > Also, I think we can use the same mechanism to program the
> > PEBS-load-latency MSR, right?
> >
> Yes, we could hardcode the latency the same way.
At least right now it would still need a constraint, because only
one counter can use it.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2010-11-12 10:48 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-11 16:15 [PATCH 1/3] perf-events: Add support for supplementary event registers Andi Kleen
2010-11-11 16:15 ` [PATCH 2/3] perf: Add support for extra parameters for raw events Andi Kleen
2010-11-11 17:54 ` Corey Ashford
2010-11-11 18:39 ` Andi Kleen
2010-11-11 19:38 ` Corey Ashford
2010-11-11 19:49 ` Andi Kleen
2010-11-11 19:59 ` Peter Zijlstra
2010-11-11 20:12 ` Andi Kleen
2010-11-11 20:37 ` Peter Zijlstra
2010-11-12 10:27 ` Andi Kleen
2010-11-12 10:49 ` Stephane Eranian
2010-11-12 11:36 ` Peter Zijlstra
2010-11-12 13:00 ` Stephane Eranian
2010-11-12 13:21 ` Peter Zijlstra
2010-11-12 14:03 ` Stephane Eranian
2010-11-12 13:30 ` Frederic Weisbecker
2010-11-12 15:00 ` Stephane Eranian
2010-11-12 10:41 ` Stephane Eranian
2010-11-12 10:48 ` Peter Zijlstra
2010-11-12 10:39 ` Stephane Eranian
2010-11-12 10:48 ` Andi Kleen [this message]
2010-11-12 10:52 ` Stephane Eranian
2010-11-12 10:56 ` Stephane Eranian
2010-11-11 16:15 ` [PATCH 3/3] perf-events: Fix LLC-* events on Intel Nehalem/Westmere Andi Kleen
2010-11-11 17:35 ` [PATCH/FIX] perf-events: Put the per cpu state for intel_pmu too Andi Kleen
2010-11-11 17:54 ` Stephane Eranian
2010-11-11 18:44 ` Andi Kleen
2010-11-11 21:29 ` Stephane Eranian
2010-11-11 18:06 ` [PATCH 1/3] perf-events: Add support for supplementary event registers Stephane Eranian
2010-11-11 18:42 ` Andi Kleen
2010-11-11 19:09 ` Peter Zijlstra
2010-11-11 19:25 ` Andi Kleen
2010-11-11 19:36 ` Peter Zijlstra
2010-11-11 19:45 ` Andi Kleen
2010-11-11 19:49 ` Peter Zijlstra
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