s3c-sdhci s3c-sdhci.1: failed to get io clock on a s3c2416

s3c-sdhci s3c-sdhci.1: failed to get io clock on a s3c2416

[Heiko Stübner]

[please keep the Cc, thanks]

Hi,

we are trying to start a current kernel on a device of the Qisda ebook-reader
family. It uses both hsmmc-channels. The first one is connected to a nand-chip
from Hynix and the second is connected to a micro-sd-slot.

The system is based on a s3c2416 soc and is the basis for nearly every ebook
reader with a sipix-display at the moment. (more than 20 different models
worldwide).

We used kernel 2.6.37rc8 with the sdhci-patch from the next-s3c24xx branch.
The first channel is initialized correctly but the second channel throws the 
error mentioned. The relevant bootlog looks like this:


s3c-sdhci s3c-sdhci.0: clock source 0: hsmmc (133333333 Hz)
s3c-sdhci s3c-sdhci.0: clock source 1: hsmmc (133333333 Hz)
s3c-sdhci s3c-sdhci.0: clock source 2: hsmmc-if (96000000 Hz)
mmc0: SDHCI controller on samsung-hsmmc [s3c-sdhci.0] using ADMA
s3c-sdhci s3c-sdhci.1: failed to get io clock
mmc0: mmc_rescan: trying to init card at 400000 Hz
s3c-sdhci: probe of s3c-sdhci.1 failed with error -2
mmc0: new high speed MMC card at address 0001
mmcblk0: mmc0:0001 HYNIX  1.88 GiB
 mmcblk0: p1 p2 p3

The complete log can be found on: http://avalon.gnuzifer.de/~fd0/oyo/bootlog

Originally Qisda used something called s3c-linux which is a fork of 2.6.21.5
implementing support for Samsung SoCs and added some (propably machine
specific) voodoo to make it work.

One source of this kernel is: http://www.thalia.de/oyo_src/SG060B00_V009.tgz

If anyone could suggest what may be wrong here I would be really grateful as 
this stuff is way out my league :-)


Thanks
Heiko

Re: s3c-sdhci s3c-sdhci.1: failed to get io clock on a s3c2416

[Heiko Stübner]

[please keep the Cc, thanks]

Am Sonntag 02 Januar 2011, 18:42:55 schrieb Heiko Stübner:
> mmc0: SDHCI controller on samsung-hsmmc [s3c-sdhci.0] using ADMA
> s3c-sdhci s3c-sdhci.1: failed to get io clock
> mmc0: mmc_rescan: trying to init card at 400000 Hz
> s3c-sdhci: probe of s3c-sdhci.1 failed with error -2
some findings by Alexander:

the smdk2416 uses arch/arm/plat-s3c24xx/s3c2443-clock.c . The clock definitions 
there don't include one for hsmmc and the needed id=1. So the second hsmmc 
channel doesn't have a clock.

Current (unsucessful)  attempts following in patch form.

Heiko

Re: s3c-sdhci s3c-sdhci.1: failed to get io clock on a s3c2416

[Heiko Stübner]

>From c3db3b64502ba991af7c51aa0571583772069db4 Mon Sep 17 00:00:00 2001
From: Alexander Neumann <alexander@bumpern.de>
Date: Sun, 2 Jan 2011 21:02:01 +0100
Subject: [PATCH] fix initialize on HSMMC channel 1

---
 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    6 ++++--
 arch/arm/mach-s3c2443/clock.c                      |   13 ++++++++-----
 arch/arm/plat-s3c24xx/s3c2443-clock.c              |    8 +++++++-
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 101aeea..bcb3090 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -86,7 +86,8 @@
 #define S3C2443_HCLKCON_LCDC		(1<<9)
 #define S3C2443_HCLKCON_USBH		(1<<11)
 #define S3C2443_HCLKCON_USBD		(1<<12)
-#define S3C2443_HCLKCON_HSMMC		(1<<16)
+#define S3C2443_HCLKCON_HSMMC1		(1<<16)
+#define S3C2443_HCLKCON_HSMMC0		(1<<15)
 #define S3C2443_HCLKCON_CFC		(1<<17)
 #define S3C2443_HCLKCON_SSMC		(1<<18)
 #define S3C2443_HCLKCON_DRAMC		(1<<19)
@@ -111,11 +112,12 @@
 #define S3C2443_SCLKCON_SSMCCLK		(1<<15)
 #define S3C2443_SCLKCON_HSSPICLK	(1<<14)
 #define S3C2443_SCLKCON_HSMMCCLK_EXT	(1<<13)
-#define S3C2443_SCLKCON_HSMMCCLK_EPLL	(1<<12)
+#define S3C2443_SCLKCON_HSMMCCLK_0	(1<<12)
 #define S3C2443_SCLKCON_CAMCLK		(1<<11)
 #define S3C2443_SCLKCON_DISPCLK		(1<<10)
 #define S3C2443_SCLKCON_I2SCLK		(1<<9)
 #define S3C2443_SCLKCON_UARTCLK		(1<<8)
+#define S3C2443_SCLKCON_HSMMCCLK_1	(1<<6)
 #define S3C2443_SCLKCON_USBHOST		(1<<1)
 
 #define S3C2443_PWRCFG_SLEEP		(1<<15)
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 0c3c0c8..65bc378 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -206,16 +206,19 @@ static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
 {
 	unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
 
+	/* reset register, disable clock for hsmmc channels 0 and 1 */
 	clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
-		    S3C2443_SCLKCON_HSMMCCLK_EPLL);
+		    S3C2443_SCLKCON_HSMMCCLK_0 |
+		    S3C2443_SCLKCON_HSMMCCLK_1);
 
-	if (parent == &clk_epll)
-		clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
-	else if (parent == &clk_ext)
+	if (parent == &clk_ext)
 		clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
-	else
+	else if (parent != &clk_epll)
 		return -EINVAL;
 
+	/* enable clock generation for hsmmc channels 0 and 1 */
+	clksrc |= S3C2443_SCLKCON_HSMMCCLK_0 | S3C2443_SCLKCON_HSMMCCLK_1;
+
 	if (clk->usage > 0) {
 		__raw_writel(clksrc, S3C2443_SCLKCON);
 	}
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 461f070..9e2ae9a 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -274,7 +274,13 @@ static struct clk init_clocks[] = {
 		.id		= 0,
 		.parent		= &clk_h,
 		.enable		= s3c2443_clkcon_enable_h,
-		.ctrlbit	= S3C2443_HCLKCON_HSMMC,
+		.ctrlbit	= S3C2443_HCLKCON_HSMMC0,
+	}, {
+		.name		= "hsmmc",
+		.id		= 1,
+		.parent		= &clk_h,
+		.enable		= s3c2443_clkcon_enable_h,
+		.ctrlbit	= S3C2443_HCLKCON_HSMMC1,
 	}, {
 		.name		= "gpio",
 		.id		= -1,
-- 
1.7.2.3