Re: [PATCH] ASoC: soc-core: Add support for NULL default register caches

[Mark Brown <broonie@opensource.wolfsonmicro.com>]

On Mon, Jan 10, 2011 at 04:40:00PM -0600, Timur Tabi wrote:

> The CS4270 registers are numbered from 1 through 8, so codec_reg should look
> like this:

>  1:   c3
>  2:    0
>  3:   30
>  4:    0
>  5:    0
>  6:    0
>  7:    0
>  8:    0

> What I don't know is why the bad output, but it's probably because the register
> cache code broke during the various changes applied to it since multi-component
> was introduced.  Originally, the driver handled the register cache completely
> internally.  Then, as register caching was added to ASoC itself, the driver was
> modified to use it.  I believe that those modifications were not really tested.

The issue is that you were using 1 based array indexing and the core
uses zero based indexing - nothing dramatically wrong and it should've
fallen through to using the hardware I/O when it went beyond the cache
so I'd expect things to work fine.  The read failure for register zero
was handled gracefully, so it looks like everything did what I'd expect
here.