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From: Timur Tabi <timur@freescale.com>
To: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>,
	alsa-devel@alsa-project.org, patches@opensource.wolfsonmicro.com,
	Liam Girdwood <lrg@slimlogic.co.uk>
Subject: Re: [PATCH] ASoC: soc-core: Add support for NULL default register caches
Date: Mon, 10 Jan 2011 16:40:00 -0600	[thread overview]
Message-ID: <4D2B8AC0.2010001@freescale.com> (raw)
In-Reply-To: <20110110222938.GD5886@opensource.wolfsonmicro.com>

Mark Brown wrote:
> You've not identified what the issue is with the above?  Is it just that
> nothing else ensured the cache was set up (eg, by doing reads from the
> hardware)?

The CS4270 registers are numbered from 1 through 8, so codec_reg should look
like this:

 1:   c3
 2:    0
 3:   30
 4:    0
 5:    0
 6:    0
 7:    0
 8:    0

What I don't know is why the bad output, but it's probably because the register
cache code broke during the various changes applied to it since multi-component
was introduced.  Originally, the driver handled the register cache completely
internally.  Then, as register caching was added to ASoC itself, the driver was
modified to use it.  I believe that those modifications were not really tested.

And since I removed all that code for my patch, I'm not really inclined to go
back and see what specifically was wrong with it.

-- 
Timur Tabi
Linux kernel developer at Freescale

  reply	other threads:[~2011-01-10 22:40 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-10 10:10 [PATCH] ASoC: soc-core: Add support for NULL default register caches Dimitris Papastamos
2011-01-10 21:48 ` Liam Girdwood
2011-01-10 22:10 ` Timur Tabi
2011-01-10 22:29   ` Mark Brown
2011-01-10 22:40     ` Timur Tabi [this message]
2011-01-10 23:48       ` Mark Brown
2011-01-10 22:25 ` Mark Brown

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