[Qemu-devel] target-sh4: improve FPU emulation

[Qemu-devel] target-sh4: improve FPU emulation

[Aurelien Jarno]

This patch series improve the FPU emulation by correctly implementing
NaN values, IEEE754 exceptions and by adding two missing instructions.

[Qemu-devel] [PATCH 1/9] target-sh4: switch sh4 to softfloat

[Aurelien Jarno]

We need to be able to catch exceptions correctly.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 configure |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/configure b/configure
index 831a741..73485c5 100755
--- a/configure
+++ b/configure
@@ -3049,7 +3049,7 @@ if test ! -z "$gdb_xml_files" ; then
 fi
 
 case "$target_arch2" in
-  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
+  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sh4|sh4eb|sparc|sparc64|sparc32plus)
     echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
     ;;
   *)
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH 1/9] target-sh4: switch sh4 to softfloat

[Nathan Froyd]

On Tue, Jan 11, 2011 at 10:01:30PM +0100, Aurelien Jarno wrote:
>  case "$target_arch2" in
> -  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
> +  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sh4|sh4eb|sparc|sparc64|sparc32plus)
>      echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
>      ;;
>    *)

This is obvious, I think...but it's also a little ridiculous.  Why not
make everything use softfloat and dispense with this?  How much work
would it be on the x86 side?

-Nathan

Re: [Qemu-devel] [PATCH 1/9] target-sh4: switch sh4 to softfloat

[Peter Maydell]

On 11 January 2011 15:22, Nathan Froyd <froydnj@codesourcery.com> wrote:
> On Tue, Jan 11, 2011 at 10:01:30PM +0100, Aurelien Jarno wrote:
>>  case "$target_arch2" in
>> -  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
>> +  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sh4|sh4eb|sparc|sparc64|sparc32plus)
>>      echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
>>      ;;
>>    *)
>
> This is obvious, I think...but it's also a little ridiculous.  Why not
> make everything use softfloat and dispense with this?  How much work
> would it be on the x86 side?

If we don't want to do that I guess we could at least change to

case "$target_arch2" in
  i386|x86_64|cris)    # I think this list is right :-)
    echo "CONFIG_NOSOFTFLOAT=y" >> $config_target_mak
    ;;
  *)
    echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
    ;;
esac

?

-- PMM

Re: [Qemu-devel] [PATCH 1/9] target-sh4: switch sh4 to softfloat

[Aurelien Jarno]

On Tue, Jan 11, 2011 at 03:35:33PM -0600, Peter Maydell wrote:
> On 11 January 2011 15:22, Nathan Froyd <froydnj@codesourcery.com> wrote:
> > On Tue, Jan 11, 2011 at 10:01:30PM +0100, Aurelien Jarno wrote:
> >>  case "$target_arch2" in
> >> -  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
> >> +  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sh4|sh4eb|sparc|sparc64|sparc32plus)
> >>      echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
> >>      ;;
> >>    *)
> >
> > This is obvious, I think...but it's also a little ridiculous.  Why not
> > make everything use softfloat and dispense with this?  How much work
> > would it be on the x86 side?
> 
> If we don't want to do that I guess we could at least change to
> 
> case "$target_arch2" in
>   i386|x86_64|cris)    # I think this list is right :-)

AFAIK, cris doesn't use fpu functions at all, so it can be in both side
without any visible effects.

>     echo "CONFIG_NOSOFTFLOAT=y" >> $config_target_mak
>     ;;
>   *)
>     echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
>     ;;
> esac
> 
> ?
> 
> -- PMM
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 1/9] target-sh4: switch sh4 to softfloat

[Edgar E. Iglesias]

On Tue, Jan 11, 2011 at 03:35:33PM -0600, Peter Maydell wrote:
> On 11 January 2011 15:22, Nathan Froyd <froydnj@codesourcery.com> wrote:
> > On Tue, Jan 11, 2011 at 10:01:30PM +0100, Aurelien Jarno wrote:
> >>  case "$target_arch2" in
> >> -  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
> >> +  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sh4|sh4eb|sparc|sparc64|sparc32plus)
> >>      echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
> >>      ;;
> >>    *)
> >
> > This is obvious, I think...but it's also a little ridiculous.  Why not
> > make everything use softfloat and dispense with this?  How much work
> > would it be on the x86 side?
> 
> If we don't want to do that I guess we could at least change to
> 
> case "$target_arch2" in
>   i386|x86_64|cris)    # I think this list is right :-)

Hi,

CRIS doesn't have an FPU so it can go aswell..

Cheers

Re: [Qemu-devel] [PATCH 1/9] target-sh4: switch sh4 to softfloat

[Aurelien Jarno]

On Tue, Jan 11, 2011 at 01:22:08PM -0800, Nathan Froyd wrote:
> On Tue, Jan 11, 2011 at 10:01:30PM +0100, Aurelien Jarno wrote:
> >  case "$target_arch2" in
> > -  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
> > +  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sh4|sh4eb|sparc|sparc64|sparc32plus)
> >      echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
> >      ;;
> >    *)
> 
> This is obvious, I think...but it's also a little ridiculous.  Why not
> make everything use softfloat and dispense with this?  How much work
> would it be on the x86 side?
> 

On the x86 target, the problem is that it doesn't compile with
softfloat. OTOH, I think it is the way to go, as for example emulating
an x86 machine on ARM, even if you don't care about the exception flags,
the precision is not correct.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

[Qemu-devel] [PATCH v2 1/9] target-sh4: switch sh4 to softfloat

[Aurelien Jarno]

We need to be able to catch exceptions correctly and thus enable softfloat
on SH4.

As all machines except i386 and x86_64 are using softfloat, make it the
default and change the case to detect i386 and x86_64. Note that CRIS
doesn't have an FPU, so it can be configured with both softfloat-native
and softfloat.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 configure |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/configure b/configure
index 438219b..473b8e9 100755
--- a/configure
+++ b/configure
@@ -3069,11 +3069,11 @@ if test ! -z "$gdb_xml_files" ; then
 fi
 
 case "$target_arch2" in
-  alpha|arm|armeb|m68k|microblaze|mips|mipsel|mipsn32|mipsn32el|mips64|mips64el|ppc|ppc64|ppc64abi32|ppcemb|s390x|sparc|sparc64|sparc32plus)
-    echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
+  i386|x86_64)
+    echo "CONFIG_NOSOFTFLOAT=y" >> $config_target_mak
     ;;
   *)
-    echo "CONFIG_NOSOFTFLOAT=y" >> $config_target_mak
+    echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
     ;;
 esac
 
-- 
1.7.2.3

[Qemu-devel] [PATCH 2/9] softfloat: SH4 has the sNaN bit set

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index f293f24..186b4da 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -30,7 +30,7 @@ these four paragraphs for those parts of this code that are retained.
 
 =============================================================================*/
 
-#if defined(TARGET_MIPS)
+#if defined(TARGET_MIPS) || defined(TARGET_SH4)
 #define SNAN_BIT_IS_ONE		1
 #else
 #define SNAN_BIT_IS_ONE		0
@@ -108,7 +108,7 @@ float32 float32_maybe_silence_nan( float32 a_ )
 {
     if (float32_is_signaling_nan(a_)) {
 #if SNAN_BIT_IS_ONE
-#  if defined(TARGET_MIPS)
+#  if defined(TARGET_MIPS) || defined(TARGET_SH4)
         return float32_default_nan;
 #  else
 #    error Rules for silencing a signaling NaN are target-specific
@@ -362,7 +362,7 @@ float64 float64_maybe_silence_nan( float64 a_ )
 {
     if (float64_is_signaling_nan(a_)) {
 #if SNAN_BIT_IS_ONE
-#  if defined(TARGET_MIPS)
+#  if defined(TARGET_MIPS) || defined(TARGET_SH4)
         return float64_default_nan;
 #  else
 #    error Rules for silencing a signaling NaN are target-specific
@@ -515,7 +515,7 @@ floatx80 floatx80_maybe_silence_nan( floatx80 a )
 {
     if (floatx80_is_signaling_nan(a)) {
 #if SNAN_BIT_IS_ONE
-#  if defined(TARGET_MIPS)
+#  if defined(TARGET_MIPS) || defined(TARGET_SH4)
         a.low = floatx80_default_nan_low;
         a.high = floatx80_default_nan_high;
 #  else
@@ -664,7 +664,7 @@ float128 float128_maybe_silence_nan( float128 a )
 {
     if (float128_is_signaling_nan(a)) {
 #if SNAN_BIT_IS_ONE
-#  if defined(TARGET_MIPS)
+#  if defined(TARGET_MIPS) || defined(TARGET_SH4)
         a.low = float128_default_nan_low;
         a.high = float128_default_nan_high;
 #  else
-- 
1.7.2.3

[Qemu-devel] [PATCH 3/9] softfloat: fix default-NaN mode

[Aurelien Jarno]

When the default-NaN mode is enabled, it should return the default NaN
value, but it should anyway raise the invalid operation flag if one of
the operand is an sNaN.

I have checked that this behavior matches the ARM and SH4 manuals, as
well as real SH4 hardware.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   36 ++++++++++++++++++------------------
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 186b4da..11521ce 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -278,9 +278,6 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
     flag aIsLargerSignificand;
     bits32 av, bv;
 
-    if ( STATUS(default_nan_mode) )
-        return float32_default_nan;
-
     aIsQuietNaN = float32_is_quiet_nan( a );
     aIsSignalingNaN = float32_is_signaling_nan( a );
     bIsQuietNaN = float32_is_quiet_nan( b );
@@ -290,6 +287,9 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
 
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
+    if ( STATUS(default_nan_mode) )
+        return float32_default_nan;
+
     if ((bits32)(av<<1) < (bits32)(bv<<1)) {
         aIsLargerSignificand = 0;
     } else if ((bits32)(bv<<1) < (bits32)(av<<1)) {
@@ -423,9 +423,6 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
     flag aIsLargerSignificand;
     bits64 av, bv;
 
-    if ( STATUS(default_nan_mode) )
-        return float64_default_nan;
-
     aIsQuietNaN = float64_is_quiet_nan( a );
     aIsSignalingNaN = float64_is_signaling_nan( a );
     bIsQuietNaN = float64_is_quiet_nan( b );
@@ -435,6 +432,9 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
 
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
+    if ( STATUS(default_nan_mode) )
+        return float64_default_nan;
+
     if ((bits64)(av<<1) < (bits64)(bv<<1)) {
         aIsLargerSignificand = 0;
     } else if ((bits64)(bv<<1) < (bits64)(av<<1)) {
@@ -574,12 +574,6 @@ static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
     flag aIsLargerSignificand;
 
-    if ( STATUS(default_nan_mode) ) {
-        a.low = floatx80_default_nan_low;
-        a.high = floatx80_default_nan_high;
-        return a;
-    }
-
     aIsQuietNaN = floatx80_is_quiet_nan( a );
     aIsSignalingNaN = floatx80_is_signaling_nan( a );
     bIsQuietNaN = floatx80_is_quiet_nan( b );
@@ -587,6 +581,12 @@ static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
 
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
+    if ( STATUS(default_nan_mode) ) {
+        a.low = floatx80_default_nan_low;
+        a.high = floatx80_default_nan_high;
+        return a;
+    }
+
     if (a.low < b.low) {
         aIsLargerSignificand = 0;
     } else if (b.low < a.low) {
@@ -719,12 +719,6 @@ static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
     flag aIsLargerSignificand;
 
-    if ( STATUS(default_nan_mode) ) {
-        a.low = float128_default_nan_low;
-        a.high = float128_default_nan_high;
-        return a;
-    }
-
     aIsQuietNaN = float128_is_quiet_nan( a );
     aIsSignalingNaN = float128_is_signaling_nan( a );
     bIsQuietNaN = float128_is_quiet_nan( b );
@@ -732,6 +726,12 @@ static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
 
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
+    if ( STATUS(default_nan_mode) ) {
+        a.low = float128_default_nan_low;
+        a.high = float128_default_nan_high;
+        return a;
+    }
+
     if (lt128(a.high<<1, a.low, b.high<<1, b.low)) {
         aIsLargerSignificand = 0;
     } else if (lt128(b.high<<1, b.low, a.high<<1, a.low)) {
-- 
1.7.2.3

[Qemu-devel] Re: [PATCH 3/9] softfloat: fix default-NaN mode

[Peter Maydell]

On 11 January 2011 15:01, Aurelien Jarno <aurelien@aurel32.net> wrote:
> When the default-NaN mode is enabled, it should return the default NaN
> value, but it should anyway raise the invalid operation flag if one of
> the operand is an sNaN.
>
> I have checked that this behavior matches the ARM and SH4 manuals, as
> well as real SH4 hardware.
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

[Qemu-devel] [PATCH 4/9] target-sh4: use default-NaN mode

[Aurelien Jarno]

SH4 FPU doesn't propagate NaN, and instead always regenerate new ones.
Enable the default-NaN mode by default.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/translate.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 155629e..8d59bf9 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -206,6 +206,7 @@ static void cpu_sh4_reset(CPUSH4State * env)
     env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 #endif
+    set_default_nan_mode(1, &env->vfp.fp_status);
     env->mmucr = 0;
 }
 
-- 
1.7.2.3

[Qemu-devel] [PATCH 5/9] target-sh4: define FPSCR constants

[Aurelien Jarno]

Define FPSCR constants for all field and use them instead of hardcoded
values.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/cpu.h       |   35 +++++++++++++++++++++++++++++++----
 target-sh4/op_helper.c |    7 ++++---
 target-sh4/translate.c |    4 ++--
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 8ccf25c..fe33b8a 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -61,10 +61,37 @@
 #define SR_S  (1 << 1)
 #define SR_T  (1 << 0)
 
-#define FPSCR_FR (1 << 21)
-#define FPSCR_SZ (1 << 20)
-#define FPSCR_PR (1 << 19)
-#define FPSCR_DN (1 << 18)
+#define FPSCR_MASK             (0x003fffff)
+#define FPSCR_FR               (1 << 21)
+#define FPSCR_SZ               (1 << 20)
+#define FPSCR_PR               (1 << 19)
+#define FPSCR_DN               (1 << 18)
+#define FPSCR_CAUSE_MASK       (0x3f << 12)
+#define FPSCR_CAUSE_SHIFT      (12)
+#define FPSCR_CAUSE_E          (1 << 17)
+#define FPSCR_CAUSE_V          (1 << 16)
+#define FPSCR_CAUSE_Z          (1 << 15)
+#define FPSCR_CAUSE_O          (1 << 14)
+#define FPSCR_CAUSE_U          (1 << 13)
+#define FPSCR_CAUSE_I          (1 << 12)
+#define FPSCR_ENABLE_MASK      (0x1f << 7)
+#define FPSCR_ENABLE_SHIFT     (7)
+#define FPSCR_ENABLE_V         (1 << 11)
+#define FPSCR_ENABLE_Z         (1 << 10)
+#define FPSCR_ENABLE_O         (1 << 9)
+#define FPSCR_ENABLE_U         (1 << 8)
+#define FPSCR_ENABLE_I         (1 << 7)
+#define FPSCR_FLAG_MASK        (0x1f << 2)
+#define FPSCR_FLAG_SHIFT       (2)
+#define FPSCR_FLAG_V           (1 << 6)
+#define FPSCR_FLAG_Z           (1 << 5)
+#define FPSCR_FLAG_O           (1 << 4)
+#define FPSCR_FLAG_U           (1 << 3)
+#define FPSCR_FLAG_I           (1 << 2)
+#define FPSCR_RM_MASK          (0x03 << 0)
+#define FPSCR_RM_NEAREST       (0 << 0)
+#define FPSCR_RM_ZERO          (1 << 0)
+
 #define DELAY_SLOT             (1 << 0)
 #define DELAY_SLOT_CONDITIONAL (1 << 1)
 #define DELAY_SLOT_TRUE        (1 << 2)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index d8d0bb4..9915e42 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -428,11 +428,12 @@ static inline void clr_t(void)
 
 void helper_ld_fpscr(uint32_t val)
 {
-    env->fpscr = val & 0x003fffff;
-    if (val & 0x01)
+    env->fpscr = val & FPSCR_MASK;
+    if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 	set_float_rounding_mode(float_round_to_zero, &env->fp_status);
-    else
+    } else {
 	set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+    }
 }
 
 uint32_t helper_fabs_FT(uint32_t t0)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 8d59bf9..bdfa31a 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -203,10 +203,10 @@ static void cpu_sh4_reset(CPUSH4State * env)
     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
 #else
-    env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
+    env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 #endif
-    set_default_nan_mode(1, &env->vfp.fp_status);
+    set_default_nan_mode(1, &env->fp_status);
     env->mmucr = 0;
 }
 
-- 
1.7.2.3

[Qemu-devel] [PATCH 6/9] target-sh4: implement flush-to-zero

[Aurelien Jarno]

When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as
zero. Enable the corresponding softfloat option when this bit is set.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/op_helper.c |    1 +
 target-sh4/translate.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 9915e42..76a40bd 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -434,6 +434,7 @@ void helper_ld_fpscr(uint32_t val)
     } else {
 	set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
     }
+    set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 }
 
 uint32_t helper_fabs_FT(uint32_t t0)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bdfa31a..080ff6e 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -205,6 +205,7 @@ static void cpu_sh4_reset(CPUSH4State * env)
 #else
     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+    set_flush_to_zero(1, &env->fp_status);
 #endif
     set_default_nan_mode(1, &env->fp_status);
     env->mmucr = 0;
-- 
1.7.2.3

[Qemu-devel] [PATCH 7/9] target-sh4: implement FPU exceptions

[Aurelien Jarno]

FPU exception support where not implemented on SH4. Implement them by
clearing the softfloat exceptions flags before an FP instruction (the
SH4 FPU also clear them before an instruction), and calling a function
to update the FPSCR register after an FP instruction. This function
update the corresponding FPSCR bits (both flags and cumulative flags)
and trigger exception if enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/op_helper.c |  158 +++++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 136 insertions(+), 22 deletions(-)

diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 76a40bd..6ab87d9 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -21,6 +21,22 @@
 #include "exec.h"
 #include "helper.h"
 
+static void cpu_restore_state_from_retaddr(void *retaddr)
+{
+    TranslationBlock *tb;
+    unsigned long pc;
+
+    if (retaddr) {
+        pc = (unsigned long) retaddr;
+        tb = tb_find_pc(pc);
+        if (tb) {
+            /* the PC is inside the translated code. It means that we have
+               a virtual CPU fault */
+            cpu_restore_state(tb, env, pc, NULL);
+        }
+    }
+}
+
 #ifndef CONFIG_USER_ONLY
 
 #define MMUSUFFIX _mmu
@@ -39,9 +55,7 @@
 
 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
 {
-    TranslationBlock *tb;
     CPUState *saved_env;
-    unsigned long pc;
     int ret;
 
     /* XXX: hack to restore env in all cases, even if not called from
@@ -50,16 +64,8 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
     env = cpu_single_env;
     ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
     if (ret) {
-	if (retaddr) {
-	    /* now we have a real cpu fault */
-	    pc = (unsigned long) retaddr;
-	    tb = tb_find_pc(pc);
-	    if (tb) {
-		/* the PC is inside the translated code. It means that we have
-		   a virtual CPU fault */
-		cpu_restore_state(tb, env, pc, NULL);
-	    }
-	}
+        /* now we have a real cpu fault */
+        cpu_restore_state_from_retaddr(retaddr);
 	cpu_loop_exit();
     }
     env = saved_env;
@@ -437,6 +443,47 @@ void helper_ld_fpscr(uint32_t val)
     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 }
 
+static void update_fpscr(void *retaddr)
+{
+    int xcpt, cause, enable;
+
+    xcpt = get_float_exception_flags(&env->fp_status);
+
+    /* Clear the flag entries */
+    env->fpscr &= ~FPSCR_FLAG_MASK;
+
+    if (unlikely(xcpt)) {
+        if (xcpt & float_flag_invalid) {
+            env->fpscr |= FPSCR_FLAG_V;
+        }
+        if (xcpt & float_flag_divbyzero) {
+            env->fpscr |= FPSCR_FLAG_Z;
+        }
+        if (xcpt & float_flag_overflow) {
+            env->fpscr |= FPSCR_FLAG_O;
+        }
+        if (xcpt & float_flag_underflow) {
+            env->fpscr |= FPSCR_FLAG_U;
+        }
+        if (xcpt & float_flag_inexact) {
+            env->fpscr |= FPSCR_FLAG_I;
+        }
+
+        /* Accumulate in cause entries */
+        env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
+                      << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
+
+        /* Generate an exception if enabled */
+        cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
+        enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
+        if (cause & enable) {
+            cpu_restore_state_from_retaddr(retaddr);
+            env->exception_index = 0x120;
+            cpu_loop_exit();
+        }
+    }
+}
+
 uint32_t helper_fabs_FT(uint32_t t0)
 {
     CPU_FloatU f;
@@ -458,7 +505,9 @@ uint32_t helper_fadd_FT(uint32_t t0, uint32_t t1)
     CPU_FloatU f0, f1;
     f0.l = t0;
     f1.l = t1;
+    set_float_exception_flags(0, &env->fp_status);
     f0.f = float32_add(f0.f, f1.f, &env->fp_status);
+    update_fpscr(GETPC());
     return f0.l;
 }
 
@@ -467,56 +516,82 @@ uint64_t helper_fadd_DT(uint64_t t0, uint64_t t1)
     CPU_DoubleU d0, d1;
     d0.ll = t0;
     d1.ll = t1;
+    set_float_exception_flags(0, &env->fp_status);
     d0.d = float64_add(d0.d, d1.d, &env->fp_status);
+    update_fpscr(GETPC());
     return d0.ll;
 }
 
 void helper_fcmp_eq_FT(uint32_t t0, uint32_t t1)
 {
     CPU_FloatU f0, f1;
+    int relation;
     f0.l = t0;
     f1.l = t1;
 
-    if (float32_compare(f0.f, f1.f, &env->fp_status) == 0)
+    set_float_exception_flags(0, &env->fp_status);
+    relation = float32_compare(f0.f, f1.f, &env->fp_status);
+    if (unlikely(relation == float_relation_unordered)) {
+        update_fpscr(GETPC());
+    } else if (relation == float_relation_equal) {
 	set_t();
-    else
+    } else {
 	clr_t();
+    }
 }
 
 void helper_fcmp_eq_DT(uint64_t t0, uint64_t t1)
 {
     CPU_DoubleU d0, d1;
+    int relation;
     d0.ll = t0;
     d1.ll = t1;
 
-    if (float64_compare(d0.d, d1.d, &env->fp_status) == 0)
+    set_float_exception_flags(0, &env->fp_status);
+    relation = float64_compare(d0.d, d1.d, &env->fp_status);
+    if (unlikely(relation == float_relation_unordered)) {
+        update_fpscr(GETPC());
+    } else if (relation == float_relation_equal) {
 	set_t();
-    else
+    } else {
 	clr_t();
+    }
 }
 
 void helper_fcmp_gt_FT(uint32_t t0, uint32_t t1)
 {
     CPU_FloatU f0, f1;
+    int relation;
     f0.l = t0;
     f1.l = t1;
 
-    if (float32_compare(f0.f, f1.f, &env->fp_status) == 1)
+    set_float_exception_flags(0, &env->fp_status);
+    relation = float32_compare(f0.f, f1.f, &env->fp_status);
+    if (unlikely(relation == float_relation_unordered)) {
+        update_fpscr(GETPC());
+    } else if (relation == float_relation_greater) {
 	set_t();
-    else
+    } else {
 	clr_t();
+    }
 }
 
 void helper_fcmp_gt_DT(uint64_t t0, uint64_t t1)
 {
     CPU_DoubleU d0, d1;
+    int relation;
     d0.ll = t0;
     d1.ll = t1;
 
-    if (float64_compare(d0.d, d1.d, &env->fp_status) == 1)
+    set_float_exception_flags(0, &env->fp_status);
+    relation = float64_compare(d0.d, d1.d, &env->fp_status);
+    if (unlikely(relation == float_relation_unordered)) {
+        update_fpscr(GETPC());
+    } else if (relation == float_relation_greater) {
 	set_t();
-    else
+    } else {
 	clr_t();
+    }
 }
 
 uint64_t helper_fcnvsd_FT_DT(uint32_t t0)
@@ -524,7 +599,9 @@ uint64_t helper_fcnvsd_FT_DT(uint32_t t0)
     CPU_DoubleU d;
     CPU_FloatU f;
     f.l = t0;
+    set_float_exception_flags(0, &env->fp_status);
     d.d = float32_to_float64(f.f, &env->fp_status);
+    update_fpscr(GETPC());
     return d.ll;
 }
 
@@ -533,7 +610,9 @@ uint32_t helper_fcnvds_DT_FT(uint64_t t0)
     CPU_DoubleU d;
     CPU_FloatU f;
     d.ll = t0;
+    set_float_exception_flags(0, &env->fp_status);
     f.f = float64_to_float32(d.d, &env->fp_status);
+    update_fpscr(GETPC());
     return f.l;
 }
 
@@ -542,7 +621,9 @@ uint32_t helper_fdiv_FT(uint32_t t0, uint32_t t1)
     CPU_FloatU f0, f1;
     f0.l = t0;
     f1.l = t1;
+    set_float_exception_flags(0, &env->fp_status);
     f0.f = float32_div(f0.f, f1.f, &env->fp_status);
+    update_fpscr(GETPC());
     return f0.l;
 }
 
@@ -551,21 +632,29 @@ uint64_t helper_fdiv_DT(uint64_t t0, uint64_t t1)
     CPU_DoubleU d0, d1;
     d0.ll = t0;
     d1.ll = t1;
+    set_float_exception_flags(0, &env->fp_status);
     d0.d = float64_div(d0.d, d1.d, &env->fp_status);
+    update_fpscr(GETPC());
     return d0.ll;
 }
 
 uint32_t helper_float_FT(uint32_t t0)
 {
     CPU_FloatU f;
+
+    set_float_exception_flags(0, &env->fp_status);
     f.f = int32_to_float32(t0, &env->fp_status);
+    update_fpscr(GETPC());
+
     return f.l;
 }
 
 uint64_t helper_float_DT(uint32_t t0)
 {
     CPU_DoubleU d;
+    set_float_exception_flags(0, &env->fp_status);
     d.d = int32_to_float64(t0, &env->fp_status);
+    update_fpscr(GETPC());
     return d.ll;
 }
 
@@ -575,8 +664,11 @@ uint32_t helper_fmac_FT(uint32_t t0, uint32_t t1, uint32_t t2)
     f0.l = t0;
     f1.l = t1;
     f2.l = t2;
+    set_float_exception_flags(0, &env->fp_status);
     f0.f = float32_mul(f0.f, f1.f, &env->fp_status);
     f0.f = float32_add(f0.f, f2.f, &env->fp_status);
+    update_fpscr(GETPC());
+
     return f0.l;
 }
 
@@ -585,7 +677,9 @@ uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1)
     CPU_FloatU f0, f1;
     f0.l = t0;
     f1.l = t1;
+    set_float_exception_flags(0, &env->fp_status);
     f0.f = float32_mul(f0.f, f1.f, &env->fp_status);
+    update_fpscr(GETPC());
     return f0.l;
 }
 
@@ -594,7 +688,10 @@ uint64_t helper_fmul_DT(uint64_t t0, uint64_t t1)
     CPU_DoubleU d0, d1;
     d0.ll = t0;
     d1.ll = t1;
+    set_float_exception_flags(0, &env->fp_status);
     d0.d = float64_mul(d0.d, d1.d, &env->fp_status);
+    update_fpscr(GETPC());
+
     return d0.ll;
 }
 
@@ -610,7 +707,9 @@ uint32_t helper_fsqrt_FT(uint32_t t0)
 {
     CPU_FloatU f;
     f.l = t0;
+    set_float_exception_flags(0, &env->fp_status);
     f.f = float32_sqrt(f.f, &env->fp_status);
+    update_fpscr(GETPC());
     return f.l;
 }
 
@@ -618,7 +717,9 @@ uint64_t helper_fsqrt_DT(uint64_t t0)
 {
     CPU_DoubleU d;
     d.ll = t0;
+    set_float_exception_flags(0, &env->fp_status);
     d.d = float64_sqrt(d.d, &env->fp_status);
+    update_fpscr(GETPC());
     return d.ll;
 }
 
@@ -627,29 +728,42 @@ uint32_t helper_fsub_FT(uint32_t t0, uint32_t t1)
     CPU_FloatU f0, f1;
     f0.l = t0;
     f1.l = t1;
+    set_float_exception_flags(0, &env->fp_status);
     f0.f = float32_sub(f0.f, f1.f, &env->fp_status);
+    update_fpscr(GETPC());
     return f0.l;
 }
 
 uint64_t helper_fsub_DT(uint64_t t0, uint64_t t1)
 {
     CPU_DoubleU d0, d1;
+
     d0.ll = t0;
     d1.ll = t1;
+    set_float_exception_flags(0, &env->fp_status);
     d0.d = float64_sub(d0.d, d1.d, &env->fp_status);
+    update_fpscr(GETPC());
     return d0.ll;
 }
 
 uint32_t helper_ftrc_FT(uint32_t t0)
 {
     CPU_FloatU f;
+    uint32_t ret;
     f.l = t0;
-    return float32_to_int32_round_to_zero(f.f, &env->fp_status);
+    set_float_exception_flags(0, &env->fp_status);
+    ret = float32_to_int32_round_to_zero(f.f, &env->fp_status);
+    update_fpscr(GETPC());
+    return ret;
 }
 
 uint32_t helper_ftrc_DT(uint64_t t0)
 {
     CPU_DoubleU d;
+    uint32_t ret;
     d.ll = t0;
-    return float64_to_int32_round_to_zero(d.d, &env->fp_status);
+    set_float_exception_flags(0, &env->fp_status);
+    ret = float64_to_int32_round_to_zero(d.d, &env->fp_status);
+    update_fpscr(GETPC());
+    return ret;
 }
-- 
1.7.2.3

[Qemu-devel] [PATCH 8/9] target-sh4: add fipr instruction

[Aurelien Jarno]

Add the fipr FVm,FVn instruction, which computes the inner products of
a 4-dimensional single precision floating-point vector.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/helper.h    |    1 +
 target-sh4/op_helper.c |   20 ++++++++++++++++++++
 target-sh4/translate.c |   12 ++++++++++++
 3 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index e4f6230..74d839f 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -48,5 +48,6 @@ DEF_HELPER_1(fsqrt_FT, i32, i32)
 DEF_HELPER_1(fsqrt_DT, i64, i64)
 DEF_HELPER_1(ftrc_FT, i32, i32)
 DEF_HELPER_1(ftrc_DT, i32, i64)
+DEF_HELPER_2(fipr, void, i32, i32)
 
 #include "def-helper.h"
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 6ab87d9..d7df3fe 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -767,3 +767,23 @@ uint32_t helper_ftrc_DT(uint64_t t0)
     update_fpscr(GETPC());
     return ret;
 }
+
+void helper_fipr(uint32_t m, uint32_t n)
+{
+    int bank, i;
+    float32 r, p;
+
+    bank = (env->sr & FPSCR_FR) ? 16 : 0;
+    r = float32_zero;
+    set_float_exception_flags(0, &env->fp_status);
+
+    for (i = 0 ; i < 4 ; i++) {
+        p = float32_mul(env->fregs[bank + m + i],
+                        env->fregs[bank + n + i],
+                        &env->fp_status);
+        r = float32_add(r, p, &env->fp_status);
+    }
+    update_fpscr(GETPC());
+
+    env->fregs[bank + n + 3] = r;
+}
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 080ff6e..566ce23 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1869,6 +1869,18 @@ static void _decode_opc(DisasContext * ctx)
 	    tcg_temp_free_i64(fp);
 	}
 	return;
+    case 0xf0ed: /* fipr FVm,FVn */
+        CHECK_FPU_ENABLED
+        if ((ctx->fpscr & FPSCR_PR) == 0) {
+            TCGv m, n;
+            m = tcg_const_i32((ctx->opcode >> 16) & 3);
+            n = tcg_const_i32((ctx->opcode >> 18) & 3);
+            gen_helper_fipr(m, n);
+            tcg_temp_free(m);
+            tcg_temp_free(n);
+            return;
+        }
+        break;
     }
 #if 0
     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
-- 
1.7.2.3

[Qemu-devel] [PATCH 9/9] target-sh4: add ftrv instruction

[Aurelien Jarno]

Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column
matrix XMTRX by the 4-dimensional vector FVn.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-sh4/helper.h    |    1 +
 target-sh4/op_helper.c |   26 ++++++++++++++++++++++++++
 target-sh4/translate.c |   11 +++++++++++
 3 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 74d839f..2e52768 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -49,5 +49,6 @@ DEF_HELPER_1(fsqrt_DT, i64, i64)
 DEF_HELPER_1(ftrc_FT, i32, i32)
 DEF_HELPER_1(ftrc_DT, i32, i64)
 DEF_HELPER_2(fipr, void, i32, i32)
+DEF_HELPER_1(ftrv, void, i32)
 
 #include "def-helper.h"
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index d7df3fe..267166b 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -787,3 +787,29 @@ void helper_fipr(uint32_t m, uint32_t n)
 
     env->fregs[bank + n + 3] = r;
 }
+
+void helper_ftrv(uint32_t n)
+{
+    int bank_matrix, bank_vector;
+    int i, j;
+    float32 r[4];
+    float32 p;
+
+    bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
+    bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
+    set_float_exception_flags(0, &env->fp_status);
+    for (i = 0 ; i < 4 ; i++) {
+        r[i] = float32_zero;
+        for (j = 0 ; j < 4 ; j++) {
+            p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
+                            env->fregs[bank_vector + j],
+                            &env->fp_status);
+            r[i] = float32_add(r[i], p, &env->fp_status);
+        }
+    }
+    update_fpscr(GETPC());
+
+    for (i = 0 ; i < 4 ; i++) {
+        env->fregs[bank_vector + i] = r[i];
+    }
+}
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 566ce23..9460a32 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1881,6 +1881,17 @@ static void _decode_opc(DisasContext * ctx)
             return;
         }
         break;
+    case 0xf0fd: /* ftrv XMTRX,FVn */
+        CHECK_FPU_ENABLED
+        if ((ctx->opcode & 0x0300) == 0x0100 &&
+            (ctx->fpscr & FPSCR_PR) == 0) {
+            TCGv n;
+            n = tcg_const_i32((ctx->opcode >> 18) & 3);
+            gen_helper_ftrv(n);
+            tcg_temp_free(n);
+            return;
+        }
+        break;
     }
 #if 0
     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
-- 
1.7.2.3