Re: [Qemu-devel] [PATCH v2 5/6] target-arm: Silence NaNs resulting from half-precision conversions

[Aurelien Jarno <aurelien@aurel32.net>]

On Wed, Feb 09, 2011 at 04:27:29PM +0000, Peter Maydell wrote:
> Silence the NaNs that may result from half-precision conversion,
> as we do for the other conversions.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/helper.c |   12 ++++++++++--
>  1 files changed, 10 insertions(+), 2 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d46defc..503278c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2627,14 +2627,22 @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
>  {
>      float_status *s = &env->vfp.fp_status;
>      int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
> -    return float16_to_float32(a, ieee, s);
> +    float32 r = float16_to_float32(a, ieee, s);
> +    if (ieee) {
> +        return float32_maybe_silence_nan(r);
> +    }
> +    return r;
>  }
>  
>  uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
>  {
>      float_status *s = &env->vfp.fp_status;
>      int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
> -    return float32_to_float16(a, ieee, s);
> +    float16 r = float32_to_float16(a, ieee, s);
> +    if (ieee) {
> +        return float16_maybe_silence_nan(r);
> +    }
> +    return r;
>  }
>  
>  float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
> -- 
> 1.7.1
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net