[U-Boot] ppc4xx PPC460EX DDR2 Autocalibration errata

[U-Boot] ppc4xx PPC460EX DDR2 Autocalibration errata

[Eibach, Dirk]

Today I received an erratum fro apm that seems to claim that ddr2
autocalibration is not working properly on our 460EX boards. Is anyone
already working on this?

Would ddr_scan_option be the way to fix this? Or should
4xx_ibm_ddr2_autocalib.c generally be fixed for 460EX?

Cheers
Dirk

DDR_2: Internal Timing violation for certain write data paths.
Category: 3
Overview:
Due to an internal timing violation, write data errors are possible with
the following MCIF0_WRDTR[WDTR]
settings:
  * 000 (270 degree advance)
  * 010 (90 degree advance)
  * 101 (180 degree delay)
  * 110 (270 degree delay)
Notes:
 1. This erratum does not affect the following MCIF0_WRDTR[WDTR]
settings:
       * 001 (180 degree advance)
       * 011 (0 degree advance)
       * 100 (90 degree delay)
 2. The timing error is internal. Write errors are possible even when
the external timing appears to be valid.
Impact:
In some cases, the memory controller fails to calibrate or pass memory
tests with MCIF0_WRDTR[WDTR] set to
the 000, 010, 101, or 110 settings. Regardless of calibration or memory
test results, write data errors are still
possible with these settings.
Workaround:
For coarse write data/DQS/DM advance or delay, only use
MCIF0_WRDTR[WDTR]=001 (180 degree advance),
011 (0 degree advance), or 100 (90 degree delay) settings. Use the
fractional fine delay MCIF0_WRDTR[WDFD]
to fine tune the delay for the Write data.
  * For 90 degree advance, set MCIF0_WRDTR[WDTR]=001 (180 degree
advance) and
     MCIF0_WRDTR[WDFD]=0x3F (90 degree delay).
  * For 180 degree delay, set MCIF0_WRDTR[WDTR]=100 (90 degree delay)
and MCIF0_WRDTR[WDFD]=0x3F
     (90 degree delay).
There are no alternative configurations for 270 degree advance or 270
degree delay.
Contact AppliedMicro technical support at support at apm.com for updated
U-Boot software.		

[U-Boot] ppc4xx PPC460EX DDR2 Autocalibration errata

[Stefan Roese]

Hi Dirk,

On Friday 11 February 2011 08:59:47 Eibach, Dirk wrote:
> Today I received an erratum fro apm that seems to claim that ddr2
> autocalibration is not working properly on our 460EX boards. Is anyone
> already working on this?

Not that I am aware of this. Perhaps somebody at AppliedMicro?
 
> Would ddr_scan_option be the way to fix this? Or should
> 4xx_ibm_ddr2_autocalib.c generally be fixed for 460EX?

Yes, ddr_scan_option() can be used to supply a board specific fix. But a 
generic fix in 4xx_ibm_ddr2_autocalib.c would be much better of course.

Do you experience any possible DDR2 related problems on your 460EX/GT based 
boards?
 
Cheers,
Stefan

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

[U-Boot] ppc4xx PPC460EX DDR2 Autocalibration errata

[Eibach, Dirk]

 

> Hi Dirk,

Hi Stefan,

> On Friday 11 February 2011 08:59:47 Eibach, Dirk wrote:
> > Today I received an erratum fro apm that seems to claim that ddr2 
> > autocalibration is not working properly on our 460EX 
> boards. Is anyone 
> > already working on this?
> 
> Not that I am aware of this. Perhaps somebody at AppliedMicro?

They offer an updated u-boot in the errata ...

> > Would ddr_scan_option be the way to fix this? Or should 
> > 4xx_ibm_ddr2_autocalib.c generally be fixed for 460EX?
> 
> Yes, ddr_scan_option() can be used to supply a board specific 
> fix. But a generic fix in 4xx_ibm_ddr2_autocalib.c would be 
> much better of course.

That's what I thought.

> Do you experience any possible DDR2 related problems on your 
> 460EX/GT based boards?

None that I am aware of. But it sounds scary anyway ...

> Cheers,
> Stefan

Cheers
Dirk