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From: Greg KH <greg@kroah.com>
To: Shaohua Li <shaohua.li@intel.com>
Cc: lkml <linux-kernel@vger.kernel.org>,
	linux-mm <linux-mm@kvack.org>, Rik van Riel <riel@redhat.com>,
	"Mallick, Asit K" <asit.k.mallick@intel.com>,
	stable <stable@kernel.org>,
	y-goto@jp.fujitsu.com, Ingo Molnar <mingo@elte.hu>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [stable] [PATCH]x86: flush tlb if PGD entry is changed in i386 PAE mode
Date: Wed, 16 Mar 2011 08:51:04 -0700	[thread overview]
Message-ID: <20110316155104.GA25008@kroah.com> (raw)
In-Reply-To: <1300246649.2337.95.camel@sli10-conroe>

On Wed, Mar 16, 2011 at 11:37:29AM +0800, Shaohua Li wrote:
> According to intel CPU manual, every time PGD entry is changed in i386 PAE mode,
> we need do a full TLB flush. Current code follows this and there is comment
> for this too in the code. But current code misses the multi-threaded case. A
> changed page table might be used by several CPUs, every such CPU should flush
> TLB.
> Usually this isn't a problem, because we prepopulate all PGD entries at process
> fork. But when the process does munmap and follows new mmap, this issue will be
> triggered. When it happens, some CPUs will keep doing page fault.
> 
> See: http://marc.info/?l=linux-kernel&m=129915020508238&w=2
> 
> Reported-by: Yasunori Goto<y-goto@jp.fujitsu.com>
> Signed-off-by: Shaohua Li<shaohua.li@intel.com>
> Tested-by: Yasunori Goto<y-goto@jp.fujitsu.com>

This is not how you submit something to the stable kernel tree.  Please
go read Documentation/stable_kernel_rules.txt for how to do it properly.

thanks,

greg k-h

WARNING: multiple messages have this Message-ID (diff)
From: Greg KH <greg@kroah.com>
To: Shaohua Li <shaohua.li@intel.com>
Cc: lkml <linux-kernel@vger.kernel.org>,
	linux-mm <linux-mm@kvack.org>, Rik van Riel <riel@redhat.com>,
	"Mallick, Asit K" <asit.k.mallick@intel.com>,
	stable <stable@kernel.org>,
	y-goto@jp.fujitsu.com, Ingo Molnar <mingo@elte.hu>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [stable] [PATCH]x86: flush tlb if PGD entry is changed in i386 PAE mode
Date: Wed, 16 Mar 2011 08:51:04 -0700	[thread overview]
Message-ID: <20110316155104.GA25008@kroah.com> (raw)
In-Reply-To: <1300246649.2337.95.camel@sli10-conroe>

On Wed, Mar 16, 2011 at 11:37:29AM +0800, Shaohua Li wrote:
> According to intel CPU manual, every time PGD entry is changed in i386 PAE mode,
> we need do a full TLB flush. Current code follows this and there is comment
> for this too in the code. But current code misses the multi-threaded case. A
> changed page table might be used by several CPUs, every such CPU should flush
> TLB.
> Usually this isn't a problem, because we prepopulate all PGD entries at process
> fork. But when the process does munmap and follows new mmap, this issue will be
> triggered. When it happens, some CPUs will keep doing page fault.
> 
> See: http://marc.info/?l=linux-kernel&m=129915020508238&w=2
> 
> Reported-by: Yasunori Goto<y-goto@jp.fujitsu.com>
> Signed-off-by: Shaohua Li<shaohua.li@intel.com>
> Tested-by: Yasunori Goto<y-goto@jp.fujitsu.com>

This is not how you submit something to the stable kernel tree.  Please
go read Documentation/stable_kernel_rules.txt for how to do it properly.

thanks,

greg k-h

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  parent reply	other threads:[~2011-03-16 15:55 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-03-16  3:37 [PATCH]x86: flush tlb if PGD entry is changed in i386 PAE mode Shaohua Li
2011-03-16  3:37 ` Shaohua Li
2011-03-16 13:03 ` Rik van Riel
2011-03-16 13:03   ` Rik van Riel
2011-03-18  2:19   ` Shaohua Li
2011-03-18  2:19     ` Shaohua Li
2011-03-16 15:51 ` Greg KH [this message]
2011-03-16 15:51   ` [stable] " Greg KH
2011-03-18 12:47 ` [tip:x86/urgent] x86: Flush TLB " tip-bot for Shaohua Li
2011-03-18 12:47   ` tip-bot for Shaohua Li

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