[Qemu-devel] [PATCH 1/5] cpu-all.h: define CPU_LDoubleU

[Qemu-devel] [PATCH 1/5] cpu-all.h: define CPU_LDoubleU

[Aurelien Jarno]

Add a CPU_LDoubleU type, matching the floatx80 definition and the long
double type on x86 hosts.

Based on a patch from Laurent Vivier <laurent@vivier.eu>.

Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-by: Aurelien Jarno <aurelien@aurel32.net>
---
 cpu-all.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index dc0f2f0..0bae6df 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -138,6 +138,16 @@ typedef union {
     uint64_t ll;
 } CPU_DoubleU;
 
+#if defined(FLOATX80)
+typedef union {
+     floatx80 d;
+     struct {
+         uint64_t lower;
+         uint16_t upper;
+     } l;
+} CPU_LDoubleU;
+#endif
+
 #if defined(CONFIG_SOFTFLOAT)
 typedef union {
     float128 q;
-- 
1.7.2.3

[Qemu-devel] [PATCH 2/5] target-i386: use CPU_LDoubleU instead of a private union

[Aurelien Jarno]

Use CPU_LDoubleU in cpu_dump_state() instead of redefining a union for
doing the conversion.

Based on a patch from Laurent Vivier <laurent@vivier.eu>.

Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-i386/helper.c |   12 +++---------
 1 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/target-i386/helper.c b/target-i386/helper.c
index d15fca5..89df997 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -404,16 +404,10 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
                     env->mxcsr);
         for(i=0;i<8;i++) {
 #if defined(USE_X86LDOUBLE)
-            union {
-                long double d;
-                struct {
-                    uint64_t lower;
-                    uint16_t upper;
-                } l;
-            } tmp;
-            tmp.d = env->fpregs[i].d;
+            CPU_LDoubleU u;
+            u.d = env->fpregs[i].d;
             cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
-                        i, tmp.l.lower, tmp.l.upper);
+                        i, u.l.lower, u.l.upper);
 #else
             cpu_fprintf(f, "FPR%d=%016" PRIx64,
                         i, env->fpregs[i].mmx.q);
-- 
1.7.2.3

[Qemu-devel] [PATCH 3/5] target-i386: fix cpu-exec.o build with softfloat

[Aurelien Jarno]

Fixing the definition of CPU86_LDoubleU allow building cpu-exec.o with
softfloat.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-i386/exec.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-i386/exec.h b/target-i386/exec.h
index 6f9f709..d6922f3 100644
--- a/target-i386/exec.h
+++ b/target-i386/exec.h
@@ -145,7 +145,7 @@ static inline void svm_check_intercept(uint32_t type)
 
 /* only for x86 */
 typedef union {
-    long double d;
+    floatx80 d;
     struct {
         unsigned long long lower;
         unsigned short upper;
@@ -164,7 +164,7 @@ typedef union {
 
 /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
 typedef union {
-    double d;
+    float64 d;
 #if !defined(HOST_WORDS_BIGENDIAN) && !defined(__arm__)
     struct {
         uint32_t lower;
-- 
1.7.2.3

[Qemu-devel] Re: [PATCH 3/5] target-i386: fix cpu-exec.o build with softfloat

[Peter Maydell]

On 10 April 2011 20:13, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Fixing the definition of CPU86_LDoubleU allow building cpu-exec.o with
> softfloat.
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-i386/exec.h |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target-i386/exec.h b/target-i386/exec.h
> index 6f9f709..d6922f3 100644
> --- a/target-i386/exec.h
> +++ b/target-i386/exec.h
> @@ -145,7 +145,7 @@ static inline void svm_check_intercept(uint32_t type)
>
>  /* only for x86 */
>  typedef union {
> -    long double d;
> +    floatx80 d;
>     struct {
>         unsigned long long lower;
>         unsigned short upper;
> @@ -164,7 +164,7 @@ typedef union {
>
>  /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
>  typedef union {
> -    double d;
> +    float64 d;
>  #if !defined(HOST_WORDS_BIGENDIAN) && !defined(__arm__)
>     struct {
>         uint32_t lower;

I note that the !USE_X86LDOUBLE typedef for CPU86_LDoubleU is an
out-of-date version of cpu-all.h's CPU_DoubleU (it doesn't
get the ARM VFP endianness right).

Given patch 1 in this series, is it possible now just to have
#ifdef USE_X86LDOUBLE
typedef CPU_LDoubleU CPU86_LDoubleU;
/* other stuff */
#else
typedef CPU_DoubleU CPU86_LDoubleU;
/* ... */
#endif

?

-- PMM

[Qemu-devel] [PATCH 4/5] softfloat: add float{32, 64, x80, 128}_unordered() functions

[Aurelien Jarno]

Add float{32,64,x80,128}_unordered() functions to softfloat, matching
the softfloat-native ones. This allow target-i386/ops_sse.h to be
compiled with softfloat.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat.c |   88 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 fpu/softfloat.h |    4 ++
 2 files changed, 92 insertions(+), 0 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 03fb948..9f94b0e 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2481,6 +2481,29 @@ int float32_lt_quiet( float32 a, float32 b STATUS_PARAM )
 }
 
 /*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float32_unordered( float32 a, float32 b STATUS_PARAM )
+{
+    a = float32_squash_input_denormal(a STATUS_VAR);
+    b = float32_squash_input_denormal(b STATUS_VAR);
+
+    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
+         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
+       ) {
+        if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
+            float_raise( float_flag_invalid STATUS_VAR);
+        }
+        return 1;
+    }
+
+    return 0;
+}
+
+/*----------------------------------------------------------------------------
 | Returns the result of converting the double-precision floating-point value
 | `a' to the 32-bit two's complement integer format.  The conversion is
 | performed according to the IEC/IEEE Standard for Binary Floating-Point
@@ -3704,6 +3727,28 @@ int float64_lt_quiet( float64 a, float64 b STATUS_PARAM )
 
 }
 
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float64_unordered( float64 a, float64 b STATUS_PARAM )
+{
+    a = float64_squash_input_denormal(a STATUS_VAR);
+    b = float64_squash_input_denormal(b STATUS_VAR);
+
+    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
+         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
+       ) {
+        if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
+            float_raise( float_flag_invalid STATUS_VAR);
+        }
+        return 0;
+    }
+    return 1;
+}
+
 #ifdef FLOATX80
 
 /*----------------------------------------------------------------------------
@@ -4695,6 +4740,27 @@ int floatx80_lt_quiet( floatx80 a, floatx80 b STATUS_PARAM )
 
 }
 
+/*----------------------------------------------------------------------------
+| Returns 1 if the extended double-precision floating-point values `a' and `b'
+| cannot be compared, and 0 otherwise. The comparison is performed according
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+int floatx80_unordered( floatx80 a, floatx80 b STATUS_PARAM )
+{
+    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
+              && (uint64_t) ( extractFloatx80Frac( a )<<1 ) )
+         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
+              && (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
+       ) {
+        if (    floatx80_is_signaling_nan( a )
+             || floatx80_is_signaling_nan( b ) ) {
+            float_raise( float_flag_invalid STATUS_VAR);
+        }
+        return 1;
+    }
+    return 0;
+}
+
 #endif
 
 #ifdef FLOAT128
@@ -5816,6 +5882,28 @@ int float128_lt_quiet( float128 a, float128 b STATUS_PARAM )
 
 }
 
+ /*----------------------------------------------------------------------------
+| Returns 1 if the quadruple-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float128_unordered( float128 a, float128 b STATUS_PARAM )
+{
+    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
+              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
+         || (    ( extractFloat128Exp( b ) == 0x7FFF )
+              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
+       ) {
+        if (    float128_is_signaling_nan( a )
+             || float128_is_signaling_nan( b ) ) {
+            float_raise( float_flag_invalid STATUS_VAR);
+        }
+        return 1;
+    }
+    return 0;
+}
+
 #endif
 
 /* misc functions */
diff --git a/fpu/softfloat.h b/fpu/softfloat.h
index 90f4250..db97be9 100644
--- a/fpu/softfloat.h
+++ b/fpu/softfloat.h
@@ -322,6 +322,7 @@ int float32_lt( float32, float32 STATUS_PARAM );
 int float32_eq_signaling( float32, float32 STATUS_PARAM );
 int float32_le_quiet( float32, float32 STATUS_PARAM );
 int float32_lt_quiet( float32, float32 STATUS_PARAM );
+int float32_unordered( float32, float32 STATUS_PARAM );
 int float32_compare( float32, float32 STATUS_PARAM );
 int float32_compare_quiet( float32, float32 STATUS_PARAM );
 float32 float32_min(float32, float32 STATUS_PARAM);
@@ -436,6 +437,7 @@ int float64_lt( float64, float64 STATUS_PARAM );
 int float64_eq_signaling( float64, float64 STATUS_PARAM );
 int float64_le_quiet( float64, float64 STATUS_PARAM );
 int float64_lt_quiet( float64, float64 STATUS_PARAM );
+int float64_unordered( float64, float64 STATUS_PARAM );
 int float64_compare( float64, float64 STATUS_PARAM );
 int float64_compare_quiet( float64, float64 STATUS_PARAM );
 float64 float64_min(float64, float64 STATUS_PARAM);
@@ -537,6 +539,7 @@ int floatx80_lt( floatx80, floatx80 STATUS_PARAM );
 int floatx80_eq_signaling( floatx80, floatx80 STATUS_PARAM );
 int floatx80_le_quiet( floatx80, floatx80 STATUS_PARAM );
 int floatx80_lt_quiet( floatx80, floatx80 STATUS_PARAM );
+int floatx80_unordered( floatx80, floatx80 STATUS_PARAM );
 int floatx80_is_quiet_nan( floatx80 );
 int floatx80_is_signaling_nan( floatx80 );
 floatx80 floatx80_maybe_silence_nan( floatx80 );
@@ -620,6 +623,7 @@ int float128_lt( float128, float128 STATUS_PARAM );
 int float128_eq_signaling( float128, float128 STATUS_PARAM );
 int float128_le_quiet( float128, float128 STATUS_PARAM );
 int float128_lt_quiet( float128, float128 STATUS_PARAM );
+int float128_unordered( float128, float128 STATUS_PARAM );
 int float128_compare( float128, float128 STATUS_PARAM );
 int float128_compare_quiet( float128, float128 STATUS_PARAM );
 int float128_is_quiet_nan( float128 );
-- 
1.7.2.3

[Qemu-devel] Re: [PATCH 4/5] softfloat: add float{32, 64, x80, 128}_unordered() functions

[Peter Maydell]

On 10 April 2011 20:13, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Add float{32,64,x80,128}_unordered() functions to softfloat, matching
> the softfloat-native ones. This allow target-i386/ops_sse.h to be
> compiled with softfloat.

I guess you could have made the x86 target use float*_compare()
instead, but I agree that it makes sense to have the unordered()
comparison to match the other specific-comparison ops.

>  /*----------------------------------------------------------------------------
> +| Returns 1 if the single-precision floating-point values `a' and `b' cannot
> +| be compared, and 0 otherwise. The comparison is performed according to the
> +| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
> +*----------------------------------------------------------------------------*/
> +
> +int float32_unordered( float32 a, float32 b STATUS_PARAM )
> +{
> +    a = float32_squash_input_denormal(a STATUS_VAR);
> +    b = float32_squash_input_denormal(b STATUS_VAR);
> +
> +    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
> +         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
> +       ) {
> +        if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
> +            float_raise( float_flag_invalid STATUS_VAR);
> +        }
> +        return 1;
> +    }
> +
> +    return 0;
> +}

So the NaN signalling semantics here are that we raise Invalid
for an SNaN but not for a QNaN. That's correct for the x86 op
we're implementing, but the float*_lt, _le and _compare functions
use the _quiet suffix for these semantics (with plain float*_lt
etc being "raise Invalid for both QNaN and SNaN"). So I think
these functions should be float*_unordered_quiet().

Annoyingly for eq the two versions use a different convention,
so we have float*_eq [raise Invalid only if SNaN] and
float*_eq_signaling [for any NaN] -- ideally that inconsistency
should be fixed...

> +int float64_unordered( float64 a, float64 b STATUS_PARAM )
> +{
> +    a = float64_squash_input_denormal(a STATUS_VAR);
> +    b = float64_squash_input_denormal(b STATUS_VAR);
> +
> +    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
> +         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
> +       ) {
> +        if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
> +            float_raise( float_flag_invalid STATUS_VAR);
> +        }
> +        return 0;
> +    }
> +    return 1;
> +}

You've got the sense the wrong way round on this one, I think.

I note that target-mips has a private float32_is_unordered()
and float64_is_unordered() which could probably be cleaned
up to use these instead. You'd need to implement both the
float*_unordered() and float*_unordered_quiet() versions.

-- PMM

Re: [Qemu-devel] Re: [PATCH 4/5] softfloat: add float{32, 64, x80, 128}_unordered() functions

[Aurelien Jarno]

On Sun, Apr 10, 2011 at 08:59:04PM +0100, Peter Maydell wrote:
> On 10 April 2011 20:13, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > Add float{32,64,x80,128}_unordered() functions to softfloat, matching
> > the softfloat-native ones. This allow target-i386/ops_sse.h to be
> > compiled with softfloat.
> 
> I guess you could have made the x86 target use float*_compare()
> instead, but I agree that it makes sense to have the unordered()
> comparison to match the other specific-comparison ops.

Given it's used in the same macro which also handle float*_le, _ge and
so on, it was easier that way. Also float*_compare() is probably a bit
slower as it does a bit more stuff.

> >  /*----------------------------------------------------------------------------
> > +| Returns 1 if the single-precision floating-point values `a' and `b' cannot
> > +| be compared, and 0 otherwise. The comparison is performed according to the
> > +| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
> > +*----------------------------------------------------------------------------*/
> > +
> > +int float32_unordered( float32 a, float32 b STATUS_PARAM )
> > +{
> > +    a = float32_squash_input_denormal(a STATUS_VAR);
> > +    b = float32_squash_input_denormal(b STATUS_VAR);
> > +
> > +    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
> > +         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
> > +       ) {
> > +        if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
> > +            float_raise( float_flag_invalid STATUS_VAR);
> > +        }
> > +        return 1;
> > +    }
> > +
> > +    return 0;
> > +}
> 
> So the NaN signalling semantics here are that we raise Invalid
> for an SNaN but not for a QNaN. That's correct for the x86 op
> we're implementing, but the float*_lt, _le and _compare functions
> use the _quiet suffix for these semantics (with plain float*_lt
> etc being "raise Invalid for both QNaN and SNaN"). So I think
> these functions should be float*_unordered_quiet().

Ok, will change that.

> Annoyingly for eq the two versions use a different convention,
> so we have float*_eq [raise Invalid only if SNaN] and
> float*_eq_signaling [for any NaN] -- ideally that inconsistency
> should be fixed...

I'll try to send a patch for that in my next version of the series.

> > +int float64_unordered( float64 a, float64 b STATUS_PARAM )
> > +{
> > +    a = float64_squash_input_denormal(a STATUS_VAR);
> > +    b = float64_squash_input_denormal(b STATUS_VAR);
> > +
> > +    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
> > +         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
> > +       ) {
> > +        if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
> > +            float_raise( float_flag_invalid STATUS_VAR);
> > +        }
> > +        return 0;
> > +    }
> > +    return 1;
> > +}
> 
> You've got the sense the wrong way round on this one, I think.

Yup, good catch.

> I note that target-mips has a private float32_is_unordered()
> and float64_is_unordered() which could probably be cleaned
> up to use these instead. You'd need to implement both the
> float*_unordered() and float*_unordered_quiet() versions.
> 

I missed that when running grep. I'll also add that in my next version
of the series (so that will be x86 + mips at the end).

Thanks for the review!

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

[Qemu-devel] [PATCH 5/5] target-i386: add floatx_{add, mul, sub} and use them

[Aurelien Jarno]

Add floatx_{add,mul,sub} defines, and use them instead of using direct
C operations.

Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-i386/exec.h      |    6 ++++++
 target-i386/op_helper.c |   18 ++++++++----------
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/target-i386/exec.h b/target-i386/exec.h
index d6922f3..6ec1a4a 100644
--- a/target-i386/exec.h
+++ b/target-i386/exec.h
@@ -110,6 +110,9 @@ static inline void svm_check_intercept(uint32_t type)
 #define float64_to_floatx float64_to_floatx80
 #define floatx_to_float32 floatx80_to_float32
 #define floatx_to_float64 floatx80_to_float64
+#define floatx_add floatx80_add
+#define floatx_mul floatx80_mul
+#define floatx_sub floatx80_sub
 #define floatx_abs floatx80_abs
 #define floatx_chs floatx80_chs
 #define floatx_round_to_int floatx80_round_to_int
@@ -126,6 +129,9 @@ static inline void svm_check_intercept(uint32_t type)
 #define float64_to_floatx(x, e) (x)
 #define floatx_to_float32 float64_to_float32
 #define floatx_to_float64(x, e) (x)
+#define floatx_add float64_add
+#define floatx_mul float64_mul
+#define floatx_sub float64_sub
 #define floatx_abs float64_abs
 #define floatx_chs float64_chs
 #define floatx_round_to_int float64_round_to_int
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 43fbd0c..a73427f 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -3711,22 +3711,22 @@ void helper_fucomi_ST0_FT0(void)
 
 void helper_fadd_ST0_FT0(void)
 {
-    ST0 += FT0;
+    ST0 = floatx_add(ST0, FT0, &env->fp_status);
 }
 
 void helper_fmul_ST0_FT0(void)
 {
-    ST0 *= FT0;
+    ST0 = floatx_mul(ST0, FT0, &env->fp_status);
 }
 
 void helper_fsub_ST0_FT0(void)
 {
-    ST0 -= FT0;
+    ST0 = floatx_sub(ST0, FT0, &env->fp_status);
 }
 
 void helper_fsubr_ST0_FT0(void)
 {
-    ST0 = FT0 - ST0;
+    ST0 = floatx_sub(FT0, ST0, &env->fp_status);
 }
 
 void helper_fdiv_ST0_FT0(void)
@@ -3743,24 +3743,22 @@ void helper_fdivr_ST0_FT0(void)
 
 void helper_fadd_STN_ST0(int st_index)
 {
-    ST(st_index) += ST0;
+    ST(st_index) = floatx_add(ST(st_index), ST0, &env->fp_status);
 }
 
 void helper_fmul_STN_ST0(int st_index)
 {
-    ST(st_index) *= ST0;
+    ST(st_index) = floatx_mul(ST(st_index), ST0, &env->fp_status);
 }
 
 void helper_fsub_STN_ST0(int st_index)
 {
-    ST(st_index) -= ST0;
+    ST(st_index) = floatx_sub(ST(st_index), ST0, &env->fp_status);
 }
 
 void helper_fsubr_STN_ST0(int st_index)
 {
-    CPU86_LDouble *p;
-    p = &ST(st_index);
-    *p = ST0 - *p;
+    ST(st_index) = floatx_sub(ST0, ST(st_index), &env->fp_status);
 }
 
 void helper_fdiv_STN_ST0(int st_index)
-- 
1.7.2.3