From: Eric B Munson <emunson@mgebm.net>
To: David Laight <David.Laight@ACULAB.COM>
Cc: a.p.zijlstra@chello.nl, linux-kernel@vger.kernel.org,
paulus@samba.org, anton@samba.org, acme@ghostprotocols.net,
mingo@elte.hu, linuxppc-dev@lists.ozlabs.org, stable@kernel.org
Subject: Re: [PATCH V4] POWER: perf_event: Skip updating kernel counters if register value shrinks
Date: Wed, 27 Apr 2011 09:20:54 -0400 [thread overview]
Message-ID: <20110427132053.GD2936@mgebm.net> (raw)
In-Reply-To: <AE90C24D6B3A694183C094C60CF0A2F6D8AD06@saturn3.aculab.com>
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On Wed, 27 Apr 2011, David Laight wrote:
>
> > prev and val are both 64 bit variables holding 32 bit numbers, we do
> not
> > accumulate in either, they are both replaced by values directly from
> the
> > registers.
> > So prev > val will not always be true.
>
> The code seems to be:
> prev = local64_read(&event->hw.prev_count);
> val = read_pmc(event->hw.idx);
> delta = check_and_compute_delta(prev, val);
> local64_add(delta, &event->count);
> Which looks very much like 'prev' being a 64bit counter generated
> from the 32bit pmc register.
>
Which implies that it will only ever be 32 bits wide, just stored in 64.
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WARNING: multiple messages have this Message-ID (diff)
From: Eric B Munson <emunson@mgebm.net>
To: David Laight <David.Laight@ACULAB.COM>
Cc: benh@kernel.crashing.org, a.p.zijlstra@chello.nl,
paulus@samba.org, mingo@elte.hu, acme@ghostprotocols.net,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
anton@samba.org, stable@kernel.org
Subject: Re: [PATCH V4] POWER: perf_event: Skip updating kernel counters if register value shrinks
Date: Wed, 27 Apr 2011 09:20:54 -0400 [thread overview]
Message-ID: <20110427132053.GD2936@mgebm.net> (raw)
In-Reply-To: <AE90C24D6B3A694183C094C60CF0A2F6D8AD06@saturn3.aculab.com>
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On Wed, 27 Apr 2011, David Laight wrote:
>
> > prev and val are both 64 bit variables holding 32 bit numbers, we do
> not
> > accumulate in either, they are both replaced by values directly from
> the
> > registers.
> > So prev > val will not always be true.
>
> The code seems to be:
> prev = local64_read(&event->hw.prev_count);
> val = read_pmc(event->hw.idx);
> delta = check_and_compute_delta(prev, val);
> local64_add(delta, &event->count);
> Which looks very much like 'prev' being a 64bit counter generated
> from the 32bit pmc register.
>
Which implies that it will only ever be 32 bits wide, just stored in 64.
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next prev parent reply other threads:[~2011-04-27 13:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-15 18:12 [PATCH V4] POWER: perf_event: Skip updating kernel counters if register value shrinks Eric B Munson
2011-04-15 18:12 ` Eric B Munson
2011-04-27 7:40 ` David Laight
2011-04-27 7:40 ` David Laight
2011-04-27 12:19 ` Eric B Munson
2011-04-27 12:19 ` Eric B Munson
2011-04-27 12:34 ` David Laight
2011-04-27 12:34 ` David Laight
2011-04-27 12:59 ` Eric B Munson
2011-04-27 12:59 ` Eric B Munson
2011-04-27 13:04 ` David Laight
2011-04-27 13:04 ` David Laight
2011-04-27 12:42 ` David Laight
2011-04-27 12:42 ` David Laight
2011-04-27 13:08 ` Eric B Munson
2011-04-27 13:08 ` Eric B Munson
2011-04-27 13:13 ` David Laight
2011-04-27 13:13 ` David Laight
2011-04-27 13:20 ` Eric B Munson [this message]
2011-04-27 13:20 ` Eric B Munson
2011-04-27 13:26 ` Benjamin Herrenschmidt
2011-04-27 13:26 ` Benjamin Herrenschmidt
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