* [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
@ 2011-08-12 9:39 ` Manuel Lauss
0 siblings, 0 replies; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss, linux-usb, Greg Kroah-Hartman
Alchemy chips have one or more registers which control access
to the usb blocks as well as PHY configuration. I don't want
the OHCI/EHCI glues to know about the different registers and bits;
new arch code hides the gory details of USB configuration from them.
Cc: linux-usb@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@suse.de> (USB glue parts)
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the
MIPS tree since other changes in it depend on it.
arch/mips/alchemy/common/Makefile | 2 +-
arch/mips/alchemy/common/dma.c | 12 +-
arch/mips/alchemy/common/power.c | 42 ----
arch/mips/alchemy/common/usb.c | 337 ++++++++++++++++++++++++++++
arch/mips/include/asm/mach-au1x00/au1000.h | 84 ++------
drivers/usb/host/ehci-au1xxx.c | 77 +------
drivers/usb/host/ohci-au1xxx.c | 110 +--------
7 files changed, 382 insertions(+), 282 deletions(-)
create mode 100644 arch/mips/alchemy/common/usb.c
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 62f0d39..31728e0 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,7 +6,7 @@
#
obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
- sleeper.o dma.o dbdma.o
+ sleeper.o dma.o dbdma.o usb.o
obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 347980e..6652a23 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -88,12 +88,12 @@ static const struct dma_dev {
{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
{ AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
{ AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
- { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
- { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
- { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
- { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
- { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
- { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
/* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 9ec8559..bdd6651 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -47,7 +47,6 @@
* We only have to save/restore registers that aren't otherwise
* done as part of a driver pm_* function.
*/
-static unsigned int sleep_usb[2];
static unsigned int sleep_sys_clocks[5];
static unsigned int sleep_sys_pinfunc;
static unsigned int sleep_static_memctlr[4][3];
@@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
static void save_core_regs(void)
{
-#ifndef CONFIG_SOC_AU1200
- /* Shutdown USB host/device. */
- sleep_usb[0] = au_readl(USB_HOST_CONFIG);
-
- /* There appears to be some undocumented reset register.... */
- au_writel(0, 0xb0100004);
- au_sync();
- au_writel(0, USB_HOST_CONFIG);
- au_sync();
-
- sleep_usb[1] = au_readl(USBD_ENABLE);
- au_writel(0, USBD_ENABLE);
- au_sync();
-
-#else /* AU1200 */
-
- /* enable access to OTG mmio so we can save OTG CAP/MUX.
- * FIXME: write an OTG driver and move this stuff there!
- */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
- sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
- sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
-#endif
-
/* Clocks and PLLs. */
sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -123,22 +97,6 @@ static void restore_core_regs(void)
au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
au_sync();
-#ifndef CONFIG_SOC_AU1200
- au_writel(sleep_usb[0], USB_HOST_CONFIG);
- au_writel(sleep_usb[1], USBD_ENABLE);
- au_sync();
-#else
- /* enable access to OTG memory */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
-
- /* restore OTG caps and port mux. */
- au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
- au_sync();
- au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
- au_sync();
-#endif
-
/* Restore the static memory controller configuration. */
au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
new file mode 100644
index 0000000..b4192c9
--- /dev/null
+++ b/arch/mips/alchemy/common/usb.c
@@ -0,0 +1,337 @@
+/*
+ * USB block power/access management abstraction.
+ *
+ * Au1000+: The OHCI block control register is at the far end of the OHCI memory
+ * area. Au1550 has OHCI on different base address. No need to handle
+ * UDC here.
+ * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
+ * as well as the PHY for EHCI and UDC.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
+#include <asm/mach-au1x00/au1000.h>
+
+/* control register offsets */
+#define AU1000_OHCICFG 0x7fffc
+#define AU1550_OHCICFG 0x07ffc
+#define AU1200_USBCFG 0x04
+
+/* Au1000 USB block config bits */
+#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
+#define USBHEN_CE (1 << 3) /* OHCI block clock enable */
+#define USBHEN_E (1 << 2) /* OHCI block enable */
+#define USBHEN_C (1 << 1) /* OHCI block coherency bit */
+#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
+
+/* Au1200 USB config bits */
+#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
+#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
+#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
+#define USBCFG_SSD (1 << 23) /* serial short detect en */
+#define USBCFG_PPE (1 << 19) /* HS PHY PLL */
+#define USBCFG_UCE (1 << 18) /* UDC clock enable */
+#define USBCFG_ECE (1 << 17) /* EHCI clock enable */
+#define USBCFG_OCE (1 << 16) /* OHCI clock enable */
+#define USBCFG_FLA(x) (((x) & 0x3f) << 8)
+#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
+#define USBCFG_GME (1 << 6) /* OTG mem access */
+#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
+#define USBCFG_DME (1 << 4) /* UDC mem enable */
+#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
+#define USBCFG_EME (1 << 2) /* EHCI mem enable */
+#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
+#define USBCFG_OME (1 << 0) /* OHCI mem enable */
+#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
+ USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
+ USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
+ USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
+ USBCFG_OME)
+
+
+static DEFINE_SPINLOCK(alchemy_usb_lock);
+
+
+static inline void __au1200_ohci_control(void __iomem *base, int enable)
+{
+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
+ if (enable) {
+ __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
+ wmb();
+ udelay(2000);
+ } else {
+ __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+ }
+}
+
+static inline void __au1200_ehci_control(void __iomem *base, int enable)
+{
+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
+ if (enable) {
+ __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+ } else {
+ if (!(r & USBCFG_UCE)) /* UDC also off? */
+ r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
+ __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+ }
+}
+
+static inline void __au1200_udc_control(void __iomem *base, int enable)
+{
+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
+ if (enable) {
+ __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
+ wmb();
+ } else {
+ if (!(r & USBCFG_ECE)) /* EHCI also off? */
+ r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
+ __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
+ wmb();
+ }
+}
+
+static inline int au1200_coherency_bug(void)
+{
+#if defined(CONFIG_DMA_COHERENT)
+ /* Au1200 AB USB does not support coherent memory */
+ if (!(read_c0_prid() & 0xff)) {
+ printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
+ printk(KERN_INFO "Au1200 USB: update your board or re-configure"
+ " the kernel\n");
+ return -ENODEV;
+ }
+#endif
+ return 0;
+}
+
+static inline int au1200_usb_control(int block, int enable)
+{
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
+ int ret = 0;
+
+ switch (block) {
+ case ALCHEMY_USB_OHCI0:
+ ret = au1200_coherency_bug();
+ if (ret && enable)
+ goto out;
+ __au1200_ohci_control(base, enable);
+ break;
+ case ALCHEMY_USB_UDC0:
+ __au1200_udc_control(base, enable);
+ break;
+ case ALCHEMY_USB_EHCI0:
+ ret = au1200_coherency_bug();
+ if (ret && enable)
+ goto out;
+ __au1200_ehci_control(base, enable);
+ break;
+ default:
+ ret = -ENODEV;
+ }
+out:
+ return ret;
+}
+
+
+/* initialize USB block(s) to a known working state */
+static inline void au1200_usb_init(void)
+{
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
+ __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+}
+
+static inline void au1000_usb_init(unsigned long rb, int reg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
+ unsigned long r = __raw_readl(base);
+
+#if defined(__BIG_ENDIAN)
+ r |= USBHEN_BE;
+#endif
+ r |= USBHEN_C;
+
+ __raw_writel(r, base);
+ wmb();
+ udelay(1000);
+}
+
+
+static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
+ unsigned long r = __raw_readl(base + creg);
+
+ if (enable) {
+ __raw_writel(r | USBHEN_CE, base + creg);
+ wmb();
+ udelay(1000);
+ __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
+ wmb();
+ udelay(1000);
+
+ /* wait for reset complete (read reg twice: au1500 erratum) */
+ while (__raw_readl(base + creg),
+ !(__raw_readl(base + creg) & USBHEN_RD))
+ udelay(1000);
+ } else {
+ __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
+ wmb();
+ }
+}
+
+static inline int au1000_usb_control(int block, int enable, unsigned long rb,
+ int creg)
+{
+ int ret = 0;
+
+ switch (block) {
+ case ALCHEMY_USB_OHCI0:
+ __au1xx0_ohci_control(enable, rb, creg);
+ break;
+ default:
+ ret = -ENODEV;
+ }
+ return ret;
+}
+
+/*
+ * alchemy_usb_control - control Alchemy on-chip USB blocks
+ * @block: USB block to target
+ * @enable: set 1 to enable a block, 0 to disable
+ */
+int alchemy_usb_control(int block, int enable)
+{
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&alchemy_usb_lock, flags);
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ ret = au1000_usb_control(block, enable,
+ AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1550:
+ ret = au1000_usb_control(block, enable,
+ AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1200:
+ ret = au1200_usb_control(block, enable);
+ break;
+ default:
+ ret = -ENODEV;
+ }
+ spin_unlock_irqrestore(&alchemy_usb_lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(alchemy_usb_control);
+
+
+static unsigned long alchemy_usb_pmdata[2];
+
+static void au1000_usb_pm(unsigned long br, int creg, int susp)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(br);
+
+ if (susp) {
+ alchemy_usb_pmdata[0] = __raw_readl(base + creg);
+ /* There appears to be some undocumented reset register.... */
+ __raw_writel(0, base + 0x04);
+ wmb();
+ __raw_writel(0, base + creg);
+ wmb();
+ } else {
+ __raw_writel(alchemy_usb_pmdata[0], base + creg);
+ wmb();
+ }
+}
+
+static void au1200_usb_pm(int susp)
+{
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
+ if (susp) {
+ /* save OTG_CAP/MUX registers which indicate port routing */
+ /* FIXME: write an OTG driver to do that */
+ alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
+ alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
+ } else {
+ /* restore access to all MMIO areas */
+ au1200_usb_init();
+
+ /* restore OTG_CAP/MUX registers */
+ __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
+ __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
+ wmb();
+ }
+}
+
+static void alchemy_usb_pm(int susp)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
+ break;
+ case ALCHEMY_CPU_AU1550:
+ au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
+ break;
+ case ALCHEMY_CPU_AU1200:
+ au1200_usb_pm(susp);
+ break;
+ }
+}
+
+static int alchemy_usb_suspend(void)
+{
+ alchemy_usb_pm(1);
+ return 0;
+}
+
+static void alchemy_usb_resume(void)
+{
+ alchemy_usb_pm(0);
+}
+
+static struct syscore_ops alchemy_usb_pm_ops = {
+ .suspend = alchemy_usb_suspend,
+ .resume = alchemy_usb_resume,
+};
+
+static int __init alchemy_usb_init(void)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1550:
+ au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1200:
+ au1200_usb_init();
+ break;
+ }
+
+ register_syscore_ops(&alchemy_usb_pm_ops);
+
+ return 0;
+}
+arch_initcall(alchemy_usb_init);
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index f260ebe..73e0d79 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -245,6 +245,15 @@ void alchemy_sleep_au1000(void);
void alchemy_sleep_au1550(void);
void au_sleep(void);
+/* USB: arch/mips/alchemy/common/usb.c */
+enum alchemy_usb_block {
+ ALCHEMY_USB_OHCI0,
+ ALCHEMY_USB_UDC0,
+ ALCHEMY_USB_EHCI0,
+ ALCHEMY_USB_OTG0,
+};
+int alchemy_usb_control(int block, int enable);
+
/* SOC Interrupt numbers */
@@ -687,7 +696,8 @@ enum soc_au1200_ints {
*/
#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
-#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */
+#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
+#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
@@ -710,12 +720,17 @@ enum soc_au1200_ints {
#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
+#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
+#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
+#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
+#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
+#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
+#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
#ifdef CONFIG_SOC_AU1000
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x10100000
#define IRDA_PHYS_ADDR 0x10300000
#define SSI0_PHYS_ADDR 0x11600000
#define SSI1_PHYS_ADDR 0x11680000
@@ -729,7 +744,6 @@ enum soc_au1200_ints {
#ifdef CONFIG_SOC_AU1500
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x10100000
#define PCI_PHYS_ADDR 0x14005000
#define PCI_MEM_PHYS_ADDR 0x400000000ULL
#define PCI_IO_PHYS_ADDR 0x500000000ULL
@@ -745,7 +759,6 @@ enum soc_au1200_ints {
#ifdef CONFIG_SOC_AU1100
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x10100000
#define IRDA_PHYS_ADDR 0x10300000
#define SSI0_PHYS_ADDR 0x11600000
#define SSI1_PHYS_ADDR 0x11680000
@@ -760,7 +773,6 @@ enum soc_au1200_ints {
#ifdef CONFIG_SOC_AU1550
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x14020000
#define PCI_PHYS_ADDR 0x14005000
#define PE_PHYS_ADDR 0x14008000
#define PSC0_PHYS_ADDR 0x11A00000
@@ -783,8 +795,6 @@ enum soc_au1200_ints {
#define STATIC_MEM_PHYS_ADDR 0x14001000
#define AES_PHYS_ADDR 0x10300000
#define CIM_PHYS_ADDR 0x14004000
-#define USBM_PHYS_ADDR 0x14020000
-#define USBH_PHYS_ADDR 0x14020100
#define PSC0_PHYS_ADDR 0x11A00000
#define PSC1_PHYS_ADDR 0x11B00000
#define LCD_PHYS_ADDR 0x15000000
@@ -868,21 +878,6 @@ enum soc_au1200_ints {
#define USB_EHCI_LEN 0x100
#define USB_UDC_BASE 0x14022000
#define USB_UDC_LEN 0x2000
-#define USB_MSR_BASE 0xB4020000
-#define USB_MSR_MCFG 4
-#define USBMSRMCFG_OMEMEN 0
-#define USBMSRMCFG_OBMEN 1
-#define USBMSRMCFG_EMEMEN 2
-#define USBMSRMCFG_EBMEN 3
-#define USBMSRMCFG_DMEMEN 4
-#define USBMSRMCFG_DBMEN 5
-#define USBMSRMCFG_GMEMEN 6
-#define USBMSRMCFG_OHCCLKEN 16
-#define USBMSRMCFG_EHCCLKEN 17
-#define USBMSRMCFG_UDCCLKEN 18
-#define USBMSRMCFG_PHYPLLEN 19
-#define USBMSRMCFG_RDCOMB 30
-#define USBMSRMCFG_PFEN 31
#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
@@ -963,51 +958,6 @@ enum soc_au1200_ints {
#define USB_OHCI_LEN 0x00100000
#endif
-#ifndef CONFIG_SOC_AU1200
-
-/* USB Device Controller */
-#define USBD_EP0RD 0xB0200000
-#define USBD_EP0WR 0xB0200004
-#define USBD_EP2WR 0xB0200008
-#define USBD_EP3WR 0xB020000C
-#define USBD_EP4RD 0xB0200010
-#define USBD_EP5RD 0xB0200014
-#define USBD_INTEN 0xB0200018
-#define USBD_INTSTAT 0xB020001C
-# define USBDEV_INT_SOF (1 << 12)
-# define USBDEV_INT_HF_BIT 6
-# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
-# define USBDEV_INT_CMPLT_BIT 0
-# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG 0xB0200020
-#define USBD_EP0CS 0xB0200024
-#define USBD_EP2CS 0xB0200028
-#define USBD_EP3CS 0xB020002C
-#define USBD_EP4CS 0xB0200030
-#define USBD_EP5CS 0xB0200034
-# define USBDEV_CS_SU (1 << 14)
-# define USBDEV_CS_NAK (1 << 13)
-# define USBDEV_CS_ACK (1 << 12)
-# define USBDEV_CS_BUSY (1 << 11)
-# define USBDEV_CS_TSIZE_BIT 1
-# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
-# define USBDEV_CS_STALL (1 << 0)
-#define USBD_EP0RDSTAT 0xB0200040
-#define USBD_EP0WRSTAT 0xB0200044
-#define USBD_EP2WRSTAT 0xB0200048
-#define USBD_EP3WRSTAT 0xB020004C
-#define USBD_EP4RDSTAT 0xB0200050
-#define USBD_EP5RDSTAT 0xB0200054
-# define USBDEV_FSTAT_FLUSH (1 << 6)
-# define USBDEV_FSTAT_UF (1 << 5)
-# define USBDEV_FSTAT_OF (1 << 4)
-# define USBDEV_FSTAT_FCNT_BIT 0
-# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE 0xB0200058
-# define USBDEV_ENABLE (1 << 1)
-# define USBDEV_CE (1 << 0)
-
-#endif /* !CONFIG_SOC_AU1200 */
/* Ethernet Controllers */
diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c
index 42ae574..e480dc1 100644
--- a/drivers/usb/host/ehci-au1xxx.c
+++ b/drivers/usb/host/ehci-au1xxx.c
@@ -14,61 +14,9 @@
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
-#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG)
-#define USB_MCFG_PFEN (1<<31)
-#define USB_MCFG_RDCOMB (1<<30)
-#define USB_MCFG_SSDEN (1<<23)
-#define USB_MCFG_PHYPLLEN (1<<19)
-#define USB_MCFG_UCECLKEN (1<<18)
-#define USB_MCFG_EHCCLKEN (1<<17)
-#ifdef CONFIG_DMA_COHERENT
-#define USB_MCFG_UCAM (1<<7)
-#else
-#define USB_MCFG_UCAM (0)
-#endif
-#define USB_MCFG_EBMEN (1<<3)
-#define USB_MCFG_EMEMEN (1<<2)
-
-#define USBH_ENABLE_CE (USB_MCFG_PHYPLLEN | USB_MCFG_EHCCLKEN)
-#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \
- USBH_ENABLE_CE | USB_MCFG_SSDEN | \
- USB_MCFG_UCAM | USB_MCFG_EBMEN | \
- USB_MCFG_EMEMEN)
-
-#define USBH_DISABLE (USB_MCFG_EBMEN | USB_MCFG_EMEMEN)
extern int usb_disabled(void);
-static void au1xxx_start_ehc(void)
-{
- /* enable clock to EHCI block and HS PHY PLL*/
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- /* enable EHCI mmio */
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-}
-
-static void au1xxx_stop_ehc(void)
-{
- unsigned long c;
-
- /* Disable mem */
- au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- /* Disable EHC clock. If the HS PHY is unused disable it too. */
- c = au_readl(USB_HOST_CONFIG) & ~USB_MCFG_EHCCLKEN;
- if (!(c & USB_MCFG_UCECLKEN)) /* UDC disabled? */
- c &= ~USB_MCFG_PHYPLLEN; /* yes: disable HS PHY PLL */
- au_writel(c, USB_HOST_CONFIG);
- au_sync();
-}
-
static int au1xxx_ehci_setup(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -136,16 +84,6 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
if (usb_disabled())
return -ENODEV;
-#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT)
- /* Au1200 AB USB does not support coherent memory */
- if (!(read_c0_prid() & 0xff)) {
- printk(KERN_INFO "%s: this is chip revision AB!\n", pdev->name);
- printk(KERN_INFO "%s: update your board or re-configure"
- " the kernel\n", pdev->name);
- return -ENODEV;
- }
-#endif
-
if (pdev->resource[1].flags != IORESOURCE_IRQ) {
pr_debug("resource[1] is not IORESOURCE_IRQ");
return -ENOMEM;
@@ -171,7 +109,11 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
goto err2;
}
- au1xxx_start_ehc();
+ if (alchemy_usb_control(ALCHEMY_USB_EHCI0, 1)) {
+ printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
+ ret = -ENODEV;
+ goto err3;
+ }
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
@@ -187,7 +129,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
return ret;
}
- au1xxx_stop_ehc();
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
+err3:
iounmap(hcd->regs);
err2:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
@@ -201,10 +144,10 @@ static int ehci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
struct usb_hcd *hcd = platform_get_drvdata(pdev);
usb_remove_hcd(hcd);
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
- au1xxx_stop_ehc();
platform_set_drvdata(pdev, NULL);
return 0;
@@ -236,7 +179,7 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev)
// could save FLADJ in case of Vaux power loss
// ... we'd only use it to handle clock skew
- au1xxx_stop_ehc();
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
return rc;
}
@@ -246,7 +189,7 @@ static int ehci_hcd_au1xxx_drv_resume(struct device *dev)
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- au1xxx_start_ehc();
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 1);
// maybe restore FLADJ
diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c
index 958d985..299d719 100644
--- a/drivers/usb/host/ohci-au1xxx.c
+++ b/drivers/usb/host/ohci-au1xxx.c
@@ -23,92 +23,9 @@
#include <asm/mach-au1x00/au1000.h>
-#ifndef CONFIG_SOC_AU1200
-
-#define USBH_ENABLE_BE (1<<0)
-#define USBH_ENABLE_C (1<<1)
-#define USBH_ENABLE_E (1<<2)
-#define USBH_ENABLE_CE (1<<3)
-#define USBH_ENABLE_RD (1<<4)
-
-#ifdef __LITTLE_ENDIAN
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
-#elif defined(__BIG_ENDIAN)
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \
- USBH_ENABLE_BE)
-#else
-#error not byte order defined
-#endif
-
-#else /* Au1200 */
-
-#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG)
-#define USB_MCFG_PFEN (1<<31)
-#define USB_MCFG_RDCOMB (1<<30)
-#define USB_MCFG_SSDEN (1<<23)
-#define USB_MCFG_OHCCLKEN (1<<16)
-#ifdef CONFIG_DMA_COHERENT
-#define USB_MCFG_UCAM (1<<7)
-#else
-#define USB_MCFG_UCAM (0)
-#endif
-#define USB_MCFG_OBMEN (1<<1)
-#define USB_MCFG_OMEMEN (1<<0)
-
-#define USBH_ENABLE_CE USB_MCFG_OHCCLKEN
-
-#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \
- USBH_ENABLE_CE | USB_MCFG_SSDEN | \
- USB_MCFG_UCAM | \
- USB_MCFG_OBMEN | USB_MCFG_OMEMEN)
-
-#define USBH_DISABLE (USB_MCFG_OBMEN | USB_MCFG_OMEMEN)
-
-#endif /* Au1200 */
extern int usb_disabled(void);
-static void au1xxx_start_ohc(void)
-{
- /* enable host controller */
-#ifndef CONFIG_SOC_AU1200
- au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- /* wait for reset complete (read register twice; see au1500 errata) */
- while (au_readl(USB_HOST_CONFIG),
- !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
- udelay(1000);
-
-#else /* Au1200 */
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG);
- au_sync();
- udelay(2000);
-#endif /* Au1200 */
-}
-
-static void au1xxx_stop_ohc(void)
-{
-#ifdef CONFIG_SOC_AU1200
- /* Disable mem */
- au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-#endif
- /* Disable clock */
- au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
-}
-
static int __devinit ohci_au1xxx_start(struct usb_hcd *hcd)
{
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
@@ -178,17 +95,6 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
if (usb_disabled())
return -ENODEV;
-#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT)
- /* Au1200 AB USB does not support coherent memory */
- if (!(read_c0_prid() & 0xff)) {
- printk(KERN_INFO "%s: this is chip revision AB !!\n",
- pdev->name);
- printk(KERN_INFO "%s: update your board or re-configure "
- "the kernel\n", pdev->name);
- return -ENODEV;
- }
-#endif
-
if (pdev->resource[1].flags != IORESOURCE_IRQ) {
pr_debug("resource[1] is not IORESOURCE_IRQ\n");
return -ENOMEM;
@@ -214,7 +120,12 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
goto err2;
}
- au1xxx_start_ohc();
+ if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) {
+ printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
+ ret = -ENODEV;
+ goto err3;
+ }
+
ohci_hcd_init(hcd_to_ohci(hcd));
ret = usb_add_hcd(hcd, pdev->resource[1].start,
@@ -224,7 +135,8 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
return ret;
}
- au1xxx_stop_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
+err3:
iounmap(hcd->regs);
err2:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
@@ -238,7 +150,7 @@ static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
struct usb_hcd *hcd = platform_get_drvdata(pdev);
usb_remove_hcd(hcd);
- au1xxx_stop_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
@@ -275,7 +187,7 @@ static int ohci_hcd_au1xxx_drv_suspend(struct device *dev)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
- au1xxx_stop_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
bail:
spin_unlock_irqrestore(&ohci->lock, flags);
@@ -286,7 +198,7 @@ static int ohci_hcd_au1xxx_drv_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
- au1xxx_start_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 1);
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
ohci_finish_controller_resume(hcd);
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
@ 2011-08-12 9:39 ` Manuel Lauss
0 siblings, 0 replies; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss, linux-usb, Greg Kroah-Hartman
Alchemy chips have one or more registers which control access
to the usb blocks as well as PHY configuration. I don't want
the OHCI/EHCI glues to know about the different registers and bits;
new arch code hides the gory details of USB configuration from them.
Cc: linux-usb@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@suse.de> (USB glue parts)
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the
MIPS tree since other changes in it depend on it.
arch/mips/alchemy/common/Makefile | 2 +-
arch/mips/alchemy/common/dma.c | 12 +-
arch/mips/alchemy/common/power.c | 42 ----
arch/mips/alchemy/common/usb.c | 337 ++++++++++++++++++++++++++++
arch/mips/include/asm/mach-au1x00/au1000.h | 84 ++------
drivers/usb/host/ehci-au1xxx.c | 77 +------
drivers/usb/host/ohci-au1xxx.c | 110 +--------
7 files changed, 382 insertions(+), 282 deletions(-)
create mode 100644 arch/mips/alchemy/common/usb.c
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 62f0d39..31728e0 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,7 +6,7 @@
#
obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
- sleeper.o dma.o dbdma.o
+ sleeper.o dma.o dbdma.o usb.o
obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 347980e..6652a23 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -88,12 +88,12 @@ static const struct dma_dev {
{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
{ AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
{ AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
- { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
- { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
- { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
- { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
- { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
- { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
+ { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
/* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 9ec8559..bdd6651 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -47,7 +47,6 @@
* We only have to save/restore registers that aren't otherwise
* done as part of a driver pm_* function.
*/
-static unsigned int sleep_usb[2];
static unsigned int sleep_sys_clocks[5];
static unsigned int sleep_sys_pinfunc;
static unsigned int sleep_static_memctlr[4][3];
@@ -55,31 +54,6 @@ static unsigned int sleep_static_memctlr[4][3];
static void save_core_regs(void)
{
-#ifndef CONFIG_SOC_AU1200
- /* Shutdown USB host/device. */
- sleep_usb[0] = au_readl(USB_HOST_CONFIG);
-
- /* There appears to be some undocumented reset register.... */
- au_writel(0, 0xb0100004);
- au_sync();
- au_writel(0, USB_HOST_CONFIG);
- au_sync();
-
- sleep_usb[1] = au_readl(USBD_ENABLE);
- au_writel(0, USBD_ENABLE);
- au_sync();
-
-#else /* AU1200 */
-
- /* enable access to OTG mmio so we can save OTG CAP/MUX.
- * FIXME: write an OTG driver and move this stuff there!
- */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
- sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
- sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
-#endif
-
/* Clocks and PLLs. */
sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
@@ -123,22 +97,6 @@ static void restore_core_regs(void)
au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
au_sync();
-#ifndef CONFIG_SOC_AU1200
- au_writel(sleep_usb[0], USB_HOST_CONFIG);
- au_writel(sleep_usb[1], USBD_ENABLE);
- au_sync();
-#else
- /* enable access to OTG memory */
- au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
- au_sync();
-
- /* restore OTG caps and port mux. */
- au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
- au_sync();
- au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
- au_sync();
-#endif
-
/* Restore the static memory controller configuration. */
au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
new file mode 100644
index 0000000..b4192c9
--- /dev/null
+++ b/arch/mips/alchemy/common/usb.c
@@ -0,0 +1,337 @@
+/*
+ * USB block power/access management abstraction.
+ *
+ * Au1000+: The OHCI block control register is at the far end of the OHCI memory
+ * area. Au1550 has OHCI on different base address. No need to handle
+ * UDC here.
+ * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
+ * as well as the PHY for EHCI and UDC.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
+#include <asm/mach-au1x00/au1000.h>
+
+/* control register offsets */
+#define AU1000_OHCICFG 0x7fffc
+#define AU1550_OHCICFG 0x07ffc
+#define AU1200_USBCFG 0x04
+
+/* Au1000 USB block config bits */
+#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
+#define USBHEN_CE (1 << 3) /* OHCI block clock enable */
+#define USBHEN_E (1 << 2) /* OHCI block enable */
+#define USBHEN_C (1 << 1) /* OHCI block coherency bit */
+#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
+
+/* Au1200 USB config bits */
+#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
+#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
+#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
+#define USBCFG_SSD (1 << 23) /* serial short detect en */
+#define USBCFG_PPE (1 << 19) /* HS PHY PLL */
+#define USBCFG_UCE (1 << 18) /* UDC clock enable */
+#define USBCFG_ECE (1 << 17) /* EHCI clock enable */
+#define USBCFG_OCE (1 << 16) /* OHCI clock enable */
+#define USBCFG_FLA(x) (((x) & 0x3f) << 8)
+#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
+#define USBCFG_GME (1 << 6) /* OTG mem access */
+#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
+#define USBCFG_DME (1 << 4) /* UDC mem enable */
+#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
+#define USBCFG_EME (1 << 2) /* EHCI mem enable */
+#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
+#define USBCFG_OME (1 << 0) /* OHCI mem enable */
+#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
+ USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
+ USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
+ USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
+ USBCFG_OME)
+
+
+static DEFINE_SPINLOCK(alchemy_usb_lock);
+
+
+static inline void __au1200_ohci_control(void __iomem *base, int enable)
+{
+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
+ if (enable) {
+ __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
+ wmb();
+ udelay(2000);
+ } else {
+ __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+ }
+}
+
+static inline void __au1200_ehci_control(void __iomem *base, int enable)
+{
+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
+ if (enable) {
+ __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+ } else {
+ if (!(r & USBCFG_UCE)) /* UDC also off? */
+ r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
+ __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+ }
+}
+
+static inline void __au1200_udc_control(void __iomem *base, int enable)
+{
+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
+ if (enable) {
+ __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
+ wmb();
+ } else {
+ if (!(r & USBCFG_ECE)) /* EHCI also off? */
+ r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
+ __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
+ wmb();
+ }
+}
+
+static inline int au1200_coherency_bug(void)
+{
+#if defined(CONFIG_DMA_COHERENT)
+ /* Au1200 AB USB does not support coherent memory */
+ if (!(read_c0_prid() & 0xff)) {
+ printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
+ printk(KERN_INFO "Au1200 USB: update your board or re-configure"
+ " the kernel\n");
+ return -ENODEV;
+ }
+#endif
+ return 0;
+}
+
+static inline int au1200_usb_control(int block, int enable)
+{
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
+ int ret = 0;
+
+ switch (block) {
+ case ALCHEMY_USB_OHCI0:
+ ret = au1200_coherency_bug();
+ if (ret && enable)
+ goto out;
+ __au1200_ohci_control(base, enable);
+ break;
+ case ALCHEMY_USB_UDC0:
+ __au1200_udc_control(base, enable);
+ break;
+ case ALCHEMY_USB_EHCI0:
+ ret = au1200_coherency_bug();
+ if (ret && enable)
+ goto out;
+ __au1200_ehci_control(base, enable);
+ break;
+ default:
+ ret = -ENODEV;
+ }
+out:
+ return ret;
+}
+
+
+/* initialize USB block(s) to a known working state */
+static inline void au1200_usb_init(void)
+{
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
+ __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
+ wmb();
+ udelay(1000);
+}
+
+static inline void au1000_usb_init(unsigned long rb, int reg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
+ unsigned long r = __raw_readl(base);
+
+#if defined(__BIG_ENDIAN)
+ r |= USBHEN_BE;
+#endif
+ r |= USBHEN_C;
+
+ __raw_writel(r, base);
+ wmb();
+ udelay(1000);
+}
+
+
+static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
+ unsigned long r = __raw_readl(base + creg);
+
+ if (enable) {
+ __raw_writel(r | USBHEN_CE, base + creg);
+ wmb();
+ udelay(1000);
+ __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
+ wmb();
+ udelay(1000);
+
+ /* wait for reset complete (read reg twice: au1500 erratum) */
+ while (__raw_readl(base + creg),
+ !(__raw_readl(base + creg) & USBHEN_RD))
+ udelay(1000);
+ } else {
+ __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
+ wmb();
+ }
+}
+
+static inline int au1000_usb_control(int block, int enable, unsigned long rb,
+ int creg)
+{
+ int ret = 0;
+
+ switch (block) {
+ case ALCHEMY_USB_OHCI0:
+ __au1xx0_ohci_control(enable, rb, creg);
+ break;
+ default:
+ ret = -ENODEV;
+ }
+ return ret;
+}
+
+/*
+ * alchemy_usb_control - control Alchemy on-chip USB blocks
+ * @block: USB block to target
+ * @enable: set 1 to enable a block, 0 to disable
+ */
+int alchemy_usb_control(int block, int enable)
+{
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&alchemy_usb_lock, flags);
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ ret = au1000_usb_control(block, enable,
+ AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1550:
+ ret = au1000_usb_control(block, enable,
+ AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1200:
+ ret = au1200_usb_control(block, enable);
+ break;
+ default:
+ ret = -ENODEV;
+ }
+ spin_unlock_irqrestore(&alchemy_usb_lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(alchemy_usb_control);
+
+
+static unsigned long alchemy_usb_pmdata[2];
+
+static void au1000_usb_pm(unsigned long br, int creg, int susp)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(br);
+
+ if (susp) {
+ alchemy_usb_pmdata[0] = __raw_readl(base + creg);
+ /* There appears to be some undocumented reset register.... */
+ __raw_writel(0, base + 0x04);
+ wmb();
+ __raw_writel(0, base + creg);
+ wmb();
+ } else {
+ __raw_writel(alchemy_usb_pmdata[0], base + creg);
+ wmb();
+ }
+}
+
+static void au1200_usb_pm(int susp)
+{
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
+ if (susp) {
+ /* save OTG_CAP/MUX registers which indicate port routing */
+ /* FIXME: write an OTG driver to do that */
+ alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
+ alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
+ } else {
+ /* restore access to all MMIO areas */
+ au1200_usb_init();
+
+ /* restore OTG_CAP/MUX registers */
+ __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
+ __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
+ wmb();
+ }
+}
+
+static void alchemy_usb_pm(int susp)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
+ break;
+ case ALCHEMY_CPU_AU1550:
+ au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
+ break;
+ case ALCHEMY_CPU_AU1200:
+ au1200_usb_pm(susp);
+ break;
+ }
+}
+
+static int alchemy_usb_suspend(void)
+{
+ alchemy_usb_pm(1);
+ return 0;
+}
+
+static void alchemy_usb_resume(void)
+{
+ alchemy_usb_pm(0);
+}
+
+static struct syscore_ops alchemy_usb_pm_ops = {
+ .suspend = alchemy_usb_suspend,
+ .resume = alchemy_usb_resume,
+};
+
+static int __init alchemy_usb_init(void)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1100:
+ au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1550:
+ au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
+ break;
+ case ALCHEMY_CPU_AU1200:
+ au1200_usb_init();
+ break;
+ }
+
+ register_syscore_ops(&alchemy_usb_pm_ops);
+
+ return 0;
+}
+arch_initcall(alchemy_usb_init);
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index f260ebe..73e0d79 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -245,6 +245,15 @@ void alchemy_sleep_au1000(void);
void alchemy_sleep_au1550(void);
void au_sleep(void);
+/* USB: arch/mips/alchemy/common/usb.c */
+enum alchemy_usb_block {
+ ALCHEMY_USB_OHCI0,
+ ALCHEMY_USB_UDC0,
+ ALCHEMY_USB_EHCI0,
+ ALCHEMY_USB_OTG0,
+};
+int alchemy_usb_control(int block, int enable);
+
/* SOC Interrupt numbers */
@@ -687,7 +696,8 @@ enum soc_au1200_ints {
*/
#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
-#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */
+#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
+#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
@@ -710,12 +720,17 @@ enum soc_au1200_ints {
#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
+#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
+#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
+#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
+#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
+#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
+#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
#ifdef CONFIG_SOC_AU1000
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x10100000
#define IRDA_PHYS_ADDR 0x10300000
#define SSI0_PHYS_ADDR 0x11600000
#define SSI1_PHYS_ADDR 0x11680000
@@ -729,7 +744,6 @@ enum soc_au1200_ints {
#ifdef CONFIG_SOC_AU1500
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x10100000
#define PCI_PHYS_ADDR 0x14005000
#define PCI_MEM_PHYS_ADDR 0x400000000ULL
#define PCI_IO_PHYS_ADDR 0x500000000ULL
@@ -745,7 +759,6 @@ enum soc_au1200_ints {
#ifdef CONFIG_SOC_AU1100
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x10100000
#define IRDA_PHYS_ADDR 0x10300000
#define SSI0_PHYS_ADDR 0x11600000
#define SSI1_PHYS_ADDR 0x11680000
@@ -760,7 +773,6 @@ enum soc_au1200_ints {
#ifdef CONFIG_SOC_AU1550
#define MEM_PHYS_ADDR 0x14000000
#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define USBH_PHYS_ADDR 0x14020000
#define PCI_PHYS_ADDR 0x14005000
#define PE_PHYS_ADDR 0x14008000
#define PSC0_PHYS_ADDR 0x11A00000
@@ -783,8 +795,6 @@ enum soc_au1200_ints {
#define STATIC_MEM_PHYS_ADDR 0x14001000
#define AES_PHYS_ADDR 0x10300000
#define CIM_PHYS_ADDR 0x14004000
-#define USBM_PHYS_ADDR 0x14020000
-#define USBH_PHYS_ADDR 0x14020100
#define PSC0_PHYS_ADDR 0x11A00000
#define PSC1_PHYS_ADDR 0x11B00000
#define LCD_PHYS_ADDR 0x15000000
@@ -868,21 +878,6 @@ enum soc_au1200_ints {
#define USB_EHCI_LEN 0x100
#define USB_UDC_BASE 0x14022000
#define USB_UDC_LEN 0x2000
-#define USB_MSR_BASE 0xB4020000
-#define USB_MSR_MCFG 4
-#define USBMSRMCFG_OMEMEN 0
-#define USBMSRMCFG_OBMEN 1
-#define USBMSRMCFG_EMEMEN 2
-#define USBMSRMCFG_EBMEN 3
-#define USBMSRMCFG_DMEMEN 4
-#define USBMSRMCFG_DBMEN 5
-#define USBMSRMCFG_GMEMEN 6
-#define USBMSRMCFG_OHCCLKEN 16
-#define USBMSRMCFG_EHCCLKEN 17
-#define USBMSRMCFG_UDCCLKEN 18
-#define USBMSRMCFG_PHYPLLEN 19
-#define USBMSRMCFG_RDCOMB 30
-#define USBMSRMCFG_PFEN 31
#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
@@ -963,51 +958,6 @@ enum soc_au1200_ints {
#define USB_OHCI_LEN 0x00100000
#endif
-#ifndef CONFIG_SOC_AU1200
-
-/* USB Device Controller */
-#define USBD_EP0RD 0xB0200000
-#define USBD_EP0WR 0xB0200004
-#define USBD_EP2WR 0xB0200008
-#define USBD_EP3WR 0xB020000C
-#define USBD_EP4RD 0xB0200010
-#define USBD_EP5RD 0xB0200014
-#define USBD_INTEN 0xB0200018
-#define USBD_INTSTAT 0xB020001C
-# define USBDEV_INT_SOF (1 << 12)
-# define USBDEV_INT_HF_BIT 6
-# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
-# define USBDEV_INT_CMPLT_BIT 0
-# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG 0xB0200020
-#define USBD_EP0CS 0xB0200024
-#define USBD_EP2CS 0xB0200028
-#define USBD_EP3CS 0xB020002C
-#define USBD_EP4CS 0xB0200030
-#define USBD_EP5CS 0xB0200034
-# define USBDEV_CS_SU (1 << 14)
-# define USBDEV_CS_NAK (1 << 13)
-# define USBDEV_CS_ACK (1 << 12)
-# define USBDEV_CS_BUSY (1 << 11)
-# define USBDEV_CS_TSIZE_BIT 1
-# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
-# define USBDEV_CS_STALL (1 << 0)
-#define USBD_EP0RDSTAT 0xB0200040
-#define USBD_EP0WRSTAT 0xB0200044
-#define USBD_EP2WRSTAT 0xB0200048
-#define USBD_EP3WRSTAT 0xB020004C
-#define USBD_EP4RDSTAT 0xB0200050
-#define USBD_EP5RDSTAT 0xB0200054
-# define USBDEV_FSTAT_FLUSH (1 << 6)
-# define USBDEV_FSTAT_UF (1 << 5)
-# define USBDEV_FSTAT_OF (1 << 4)
-# define USBDEV_FSTAT_FCNT_BIT 0
-# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE 0xB0200058
-# define USBDEV_ENABLE (1 << 1)
-# define USBDEV_CE (1 << 0)
-
-#endif /* !CONFIG_SOC_AU1200 */
/* Ethernet Controllers */
diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c
index 42ae574..e480dc1 100644
--- a/drivers/usb/host/ehci-au1xxx.c
+++ b/drivers/usb/host/ehci-au1xxx.c
@@ -14,61 +14,9 @@
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
-#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG)
-#define USB_MCFG_PFEN (1<<31)
-#define USB_MCFG_RDCOMB (1<<30)
-#define USB_MCFG_SSDEN (1<<23)
-#define USB_MCFG_PHYPLLEN (1<<19)
-#define USB_MCFG_UCECLKEN (1<<18)
-#define USB_MCFG_EHCCLKEN (1<<17)
-#ifdef CONFIG_DMA_COHERENT
-#define USB_MCFG_UCAM (1<<7)
-#else
-#define USB_MCFG_UCAM (0)
-#endif
-#define USB_MCFG_EBMEN (1<<3)
-#define USB_MCFG_EMEMEN (1<<2)
-
-#define USBH_ENABLE_CE (USB_MCFG_PHYPLLEN | USB_MCFG_EHCCLKEN)
-#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \
- USBH_ENABLE_CE | USB_MCFG_SSDEN | \
- USB_MCFG_UCAM | USB_MCFG_EBMEN | \
- USB_MCFG_EMEMEN)
-
-#define USBH_DISABLE (USB_MCFG_EBMEN | USB_MCFG_EMEMEN)
extern int usb_disabled(void);
-static void au1xxx_start_ehc(void)
-{
- /* enable clock to EHCI block and HS PHY PLL*/
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- /* enable EHCI mmio */
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-}
-
-static void au1xxx_stop_ehc(void)
-{
- unsigned long c;
-
- /* Disable mem */
- au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- /* Disable EHC clock. If the HS PHY is unused disable it too. */
- c = au_readl(USB_HOST_CONFIG) & ~USB_MCFG_EHCCLKEN;
- if (!(c & USB_MCFG_UCECLKEN)) /* UDC disabled? */
- c &= ~USB_MCFG_PHYPLLEN; /* yes: disable HS PHY PLL */
- au_writel(c, USB_HOST_CONFIG);
- au_sync();
-}
-
static int au1xxx_ehci_setup(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -136,16 +84,6 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
if (usb_disabled())
return -ENODEV;
-#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT)
- /* Au1200 AB USB does not support coherent memory */
- if (!(read_c0_prid() & 0xff)) {
- printk(KERN_INFO "%s: this is chip revision AB!\n", pdev->name);
- printk(KERN_INFO "%s: update your board or re-configure"
- " the kernel\n", pdev->name);
- return -ENODEV;
- }
-#endif
-
if (pdev->resource[1].flags != IORESOURCE_IRQ) {
pr_debug("resource[1] is not IORESOURCE_IRQ");
return -ENOMEM;
@@ -171,7 +109,11 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
goto err2;
}
- au1xxx_start_ehc();
+ if (alchemy_usb_control(ALCHEMY_USB_EHCI0, 1)) {
+ printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
+ ret = -ENODEV;
+ goto err3;
+ }
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
@@ -187,7 +129,8 @@ static int ehci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
return ret;
}
- au1xxx_stop_ehc();
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
+err3:
iounmap(hcd->regs);
err2:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
@@ -201,10 +144,10 @@ static int ehci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
struct usb_hcd *hcd = platform_get_drvdata(pdev);
usb_remove_hcd(hcd);
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
- au1xxx_stop_ehc();
platform_set_drvdata(pdev, NULL);
return 0;
@@ -236,7 +179,7 @@ static int ehci_hcd_au1xxx_drv_suspend(struct device *dev)
// could save FLADJ in case of Vaux power loss
// ... we'd only use it to handle clock skew
- au1xxx_stop_ehc();
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
return rc;
}
@@ -246,7 +189,7 @@ static int ehci_hcd_au1xxx_drv_resume(struct device *dev)
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
- au1xxx_start_ehc();
+ alchemy_usb_control(ALCHEMY_USB_EHCI0, 1);
// maybe restore FLADJ
diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c
index 958d985..299d719 100644
--- a/drivers/usb/host/ohci-au1xxx.c
+++ b/drivers/usb/host/ohci-au1xxx.c
@@ -23,92 +23,9 @@
#include <asm/mach-au1x00/au1000.h>
-#ifndef CONFIG_SOC_AU1200
-
-#define USBH_ENABLE_BE (1<<0)
-#define USBH_ENABLE_C (1<<1)
-#define USBH_ENABLE_E (1<<2)
-#define USBH_ENABLE_CE (1<<3)
-#define USBH_ENABLE_RD (1<<4)
-
-#ifdef __LITTLE_ENDIAN
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
-#elif defined(__BIG_ENDIAN)
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | \
- USBH_ENABLE_BE)
-#else
-#error not byte order defined
-#endif
-
-#else /* Au1200 */
-
-#define USB_HOST_CONFIG (USB_MSR_BASE + USB_MSR_MCFG)
-#define USB_MCFG_PFEN (1<<31)
-#define USB_MCFG_RDCOMB (1<<30)
-#define USB_MCFG_SSDEN (1<<23)
-#define USB_MCFG_OHCCLKEN (1<<16)
-#ifdef CONFIG_DMA_COHERENT
-#define USB_MCFG_UCAM (1<<7)
-#else
-#define USB_MCFG_UCAM (0)
-#endif
-#define USB_MCFG_OBMEN (1<<1)
-#define USB_MCFG_OMEMEN (1<<0)
-
-#define USBH_ENABLE_CE USB_MCFG_OHCCLKEN
-
-#define USBH_ENABLE_INIT (USB_MCFG_PFEN | USB_MCFG_RDCOMB | \
- USBH_ENABLE_CE | USB_MCFG_SSDEN | \
- USB_MCFG_UCAM | \
- USB_MCFG_OBMEN | USB_MCFG_OMEMEN)
-
-#define USBH_DISABLE (USB_MCFG_OBMEN | USB_MCFG_OMEMEN)
-
-#endif /* Au1200 */
extern int usb_disabled(void);
-static void au1xxx_start_ohc(void)
-{
- /* enable host controller */
-#ifndef CONFIG_SOC_AU1200
- au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- /* wait for reset complete (read register twice; see au1500 errata) */
- while (au_readl(USB_HOST_CONFIG),
- !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
- udelay(1000);
-
-#else /* Au1200 */
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-
- au_writel(au_readl(USB_HOST_CONFIG) | USBH_ENABLE_INIT, USB_HOST_CONFIG);
- au_sync();
- udelay(2000);
-#endif /* Au1200 */
-}
-
-static void au1xxx_stop_ohc(void)
-{
-#ifdef CONFIG_SOC_AU1200
- /* Disable mem */
- au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_DISABLE, USB_HOST_CONFIG);
- au_sync();
- udelay(1000);
-#endif
- /* Disable clock */
- au_writel(au_readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
- au_sync();
-}
-
static int __devinit ohci_au1xxx_start(struct usb_hcd *hcd)
{
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
@@ -178,17 +95,6 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
if (usb_disabled())
return -ENODEV;
-#if defined(CONFIG_SOC_AU1200) && defined(CONFIG_DMA_COHERENT)
- /* Au1200 AB USB does not support coherent memory */
- if (!(read_c0_prid() & 0xff)) {
- printk(KERN_INFO "%s: this is chip revision AB !!\n",
- pdev->name);
- printk(KERN_INFO "%s: update your board or re-configure "
- "the kernel\n", pdev->name);
- return -ENODEV;
- }
-#endif
-
if (pdev->resource[1].flags != IORESOURCE_IRQ) {
pr_debug("resource[1] is not IORESOURCE_IRQ\n");
return -ENOMEM;
@@ -214,7 +120,12 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
goto err2;
}
- au1xxx_start_ohc();
+ if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) {
+ printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
+ ret = -ENODEV;
+ goto err3;
+ }
+
ohci_hcd_init(hcd_to_ohci(hcd));
ret = usb_add_hcd(hcd, pdev->resource[1].start,
@@ -224,7 +135,8 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
return ret;
}
- au1xxx_stop_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
+err3:
iounmap(hcd->regs);
err2:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
@@ -238,7 +150,7 @@ static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
struct usb_hcd *hcd = platform_get_drvdata(pdev);
usb_remove_hcd(hcd);
- au1xxx_stop_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
@@ -275,7 +187,7 @@ static int ohci_hcd_au1xxx_drv_suspend(struct device *dev)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
- au1xxx_stop_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
bail:
spin_unlock_irqrestore(&ohci->lock, flags);
@@ -286,7 +198,7 @@ static int ohci_hcd_au1xxx_drv_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
- au1xxx_start_ohc();
+ alchemy_usb_control(ALCHEMY_USB_OHCI0, 1);
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
ohci_finish_controller_resume(hcd);
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
2011-08-12 9:39 ` Manuel Lauss
(?)
@ 2011-08-12 16:04 ` Greg KH
2011-08-12 16:20 ` Manuel Lauss
-1 siblings, 1 reply; 21+ messages in thread
From: Greg KH @ 2011-08-12 16:04 UTC (permalink / raw)
To: Manuel Lauss; +Cc: Linux-MIPS, Ralf Baechle, linux-usb
On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote:
> Alchemy chips have one or more registers which control access
> to the usb blocks as well as PHY configuration. I don't want
> the OHCI/EHCI glues to know about the different registers and bits;
> new arch code hides the gory details of USB configuration from them.
>
> Cc: linux-usb@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@suse.de> (USB glue parts)
> Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
> ---
> CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the
> MIPS tree since other changes in it depend on it.
Fine with me on the USB portions, you are just deleting code, which I
like :)
But should the "common" USB code really live under arch/mips/alchemy/ ?
The goal is to move driver code out of arch/ and into drivers/. Why are
you moving stuff backwards here?
greg k-h
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
2011-08-12 16:04 ` Greg KH
@ 2011-08-12 16:20 ` Manuel Lauss
2011-08-12 16:33 ` Greg KH
0 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 16:20 UTC (permalink / raw)
To: Greg KH; +Cc: Linux-MIPS, Ralf Baechle, linux-usb
On Fri, Aug 12, 2011 at 6:04 PM, Greg KH <gregkh@suse.de> wrote:
> On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote:
>> Alchemy chips have one or more registers which control access
>> to the usb blocks as well as PHY configuration. I don't want
>> the OHCI/EHCI glues to know about the different registers and bits;
>> new arch code hides the gory details of USB configuration from them.
>>
>> Cc: linux-usb@vger.kernel.org
>> Cc: Greg Kroah-Hartman <gregkh@suse.de> (USB glue parts)
>> Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
>> ---
>> CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the
>> MIPS tree since other changes in it depend on it.
>
> Fine with me on the USB portions, you are just deleting code, which I
> like :)
Thanks!
> But should the "common" USB code really live under arch/mips/alchemy/ ?
> The goal is to move driver code out of arch/ and into drivers/. Why are
> you moving stuff backwards here?
This is just chip-dependent code for usb block and phy management, which
varies wich chip subtype, the OHCI and EHCI controllers are identical on all
of them. At the time moving the chip-depedent code to the other chip-dependent
code seemed like a good idea...
Manuel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
2011-08-12 16:20 ` Manuel Lauss
@ 2011-08-12 16:33 ` Greg KH
2011-08-12 17:25 ` Manuel Lauss
2011-08-12 17:27 ` Ralf Baechle
0 siblings, 2 replies; 21+ messages in thread
From: Greg KH @ 2011-08-12 16:33 UTC (permalink / raw)
To: Manuel Lauss; +Cc: Linux-MIPS, Ralf Baechle, linux-usb
On Fri, Aug 12, 2011 at 06:20:48PM +0200, Manuel Lauss wrote:
> On Fri, Aug 12, 2011 at 6:04 PM, Greg KH <gregkh@suse.de> wrote:
> > On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote:
> >> Alchemy chips have one or more registers which control access
> >> to the usb blocks as well as PHY configuration. I don't want
> >> the OHCI/EHCI glues to know about the different registers and bits;
> >> new arch code hides the gory details of USB configuration from them.
> >>
> >> Cc: linux-usb@vger.kernel.org
> >> Cc: Greg Kroah-Hartman <gregkh@suse.de> (USB glue parts)
> >> Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
> >> ---
> >> CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the
> >> MIPS tree since other changes in it depend on it.
> >
> > Fine with me on the USB portions, you are just deleting code, which I
> > like :)
>
> Thanks!
>
>
> > But should the "common" USB code really live under arch/mips/alchemy/ ?
> > The goal is to move driver code out of arch/ and into drivers/. Why are
> > you moving stuff backwards here?
>
> This is just chip-dependent code for usb block and phy management, which
> varies wich chip subtype, the OHCI and EHCI controllers are identical on all
> of them. At the time moving the chip-depedent code to the other chip-dependent
> code seemed like a good idea...
But that's what drivers/* is, chip-dependent code. Please move it there
instead.
Has the MIPS developers learned nothing from the recent ARM mess? :)
greg k-h
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
2011-08-12 16:33 ` Greg KH
@ 2011-08-12 17:25 ` Manuel Lauss
2011-08-12 17:27 ` Ralf Baechle
1 sibling, 0 replies; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 17:25 UTC (permalink / raw)
To: Greg KH; +Cc: Linux-MIPS, Ralf Baechle, linux-usb
On Fri, Aug 12, 2011 at 6:33 PM, Greg KH <gregkh@suse.de> wrote:
> On Fri, Aug 12, 2011 at 06:20:48PM +0200, Manuel Lauss wrote:
>> On Fri, Aug 12, 2011 at 6:04 PM, Greg KH <gregkh@suse.de> wrote:
>> > On Fri, Aug 12, 2011 at 11:39:38AM +0200, Manuel Lauss wrote:
>> >> Alchemy chips have one or more registers which control access
>> >> to the usb blocks as well as PHY configuration. I don't want
>> >> the OHCI/EHCI glues to know about the different registers and bits;
>> >> new arch code hides the gory details of USB configuration from them.
>> >>
>> >> Cc: linux-usb@vger.kernel.org
>> >> Cc: Greg Kroah-Hartman <gregkh@suse.de> (USB glue parts)
>> >> Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
>> >> ---
>> >> CC'ed Greg for an Ack on the USB glue parts. I'd like this to go through the
>> >> MIPS tree since other changes in it depend on it.
>> >
>> > Fine with me on the USB portions, you are just deleting code, which I
>> > like :)
>>
>> Thanks!
>>
>>
>> > But should the "common" USB code really live under arch/mips/alchemy/ ?
>> > The goal is to move driver code out of arch/ and into drivers/. Why are
>> > you moving stuff backwards here?
>>
>> This is just chip-dependent code for usb block and phy management, which
>> varies wich chip subtype, the OHCI and EHCI controllers are identical on all
>> of them. At the time moving the chip-depedent code to the other chip-dependent
>> code seemed like a good idea...
>
> But that's what drivers/* is, chip-dependent code. Please move it there
> instead.
>
> Has the MIPS developers learned nothing from the recent ARM mess? :)
Personally I disagree with some of the results of the "ARM mess", but if that's
what it takes to get things moving forware, so be it.
Give me a few minutes to figure out what to do...
Thanks!
Manuel
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 1/8] MIPS: Alchemy: abstract USB block control register access
2011-08-12 16:33 ` Greg KH
2011-08-12 17:25 ` Manuel Lauss
@ 2011-08-12 17:27 ` Ralf Baechle
1 sibling, 0 replies; 21+ messages in thread
From: Ralf Baechle @ 2011-08-12 17:27 UTC (permalink / raw)
To: Greg KH; +Cc: Manuel Lauss, Linux-MIPS, linux-usb
On Fri, Aug 12, 2011 at 09:33:25AM -0700, Greg KH wrote:
> Has the MIPS developers learned nothing from the recent ARM mess? :)
The MIPS maintainer was scratching his head over the point of this series :)
Ralf
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/8] MIPS: Alchemy: rewrite USB platform setup.
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
2011-08-12 9:39 ` Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-15 13:24 ` Ralf Baechle
2011-08-12 9:39 ` [PATCH 3/8] MIPS: Alchemy: more base address cleanup Manuel Lauss
` (5 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss
Use runtime CPU detection to setup all USB parts.
Remove the Au1200 OTG and UDC platform devices since there are no
drivers for them anyway.
Clean up the USB address mess in the au1000 header.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
arch/mips/alchemy/common/platform.c | 183 +++++++++++----------------
arch/mips/include/asm/mach-au1x00/au1000.h | 55 ---------
2 files changed, 75 insertions(+), 163 deletions(-)
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 15d9b2f..910a3bd 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -111,34 +111,84 @@ static void __init alchemy_setup_uarts(int ctype)
printk(KERN_INFO "Alchemy: failed to register UARTs\n");
}
-/* OHCI (USB full speed host controller) */
-static struct resource au1xxx_usb_ohci_resources[] = {
- [0] = {
- .start = USB_OHCI_BASE,
- .end = USB_OHCI_BASE + USB_OHCI_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = FOR_PLATFORM_C_USB_HOST_INT,
- .end = FOR_PLATFORM_C_USB_HOST_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
+/* The dmamask must be set for OHCI/EHCI to work */
+static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
+static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
-static struct platform_device au1xxx_usb_ohci_device = {
- .name = "au1xxx-ohci",
- .id = 0,
- .dev = {
- .dma_mask = &ohci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
- .resource = au1xxx_usb_ohci_resources,
+static unsigned long alchemy_ohci_data[][2] __initdata = {
+ [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
+ [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
+};
+
+static unsigned long alchemy_ehci_data[][2] __initdata = {
+ [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
};
+static int __init _new_usbres(struct resource **r, struct platform_device **d)
+{
+ *r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ if (!*r)
+ return -ENOMEM;
+ *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
+ if (!*d) {
+ kfree(*r);
+ return -ENOMEM;
+ }
+
+ (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ (*d)->num_resources = 2;
+ (*d)->resource = *r;
+
+ return 0;
+}
+
+static void __init alchemy_setup_usb(int ctype)
+{
+ struct resource *res;
+ struct platform_device *pdev;
+
+ /* setup OHCI0. Every variant has one */
+ if (_new_usbres(&res, &pdev))
+ return;
+
+ res[0].start = alchemy_ohci_data[ctype][0];
+ res[0].end = res[0].start + 0x100 - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = alchemy_ohci_data[ctype][1];
+ res[1].end = res[1].start;
+ res[1].flags = IORESOURCE_IRQ;
+ pdev->name = "au1xxx-ohci";
+ pdev->id = 0;
+ pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+
+ if (platform_device_register(pdev))
+ printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
+
+
+ /* setup EHCI0: Au1200 */
+ if (ctype == ALCHEMY_CPU_AU1200) {
+ if (_new_usbres(&res, &pdev))
+ return;
+
+ res[0].start = alchemy_ehci_data[ctype][0];
+ res[0].end = res[0].start + 0x100 - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = alchemy_ehci_data[ctype][1];
+ res[1].end = res[1].start;
+ res[1].flags = IORESOURCE_IRQ;
+ pdev->name = "au1xxx-ehci";
+ pdev->id = 0;
+ pdev->dev.dma_mask = &alchemy_ehci_dmamask;
+
+ if (platform_device_register(pdev))
+ printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
+ }
+}
+
/*** AU1100 LCD controller ***/
#ifdef CONFIG_FB_AU1100
@@ -170,86 +220,6 @@ static struct platform_device au1100_lcd_device = {
#endif
#ifdef CONFIG_SOC_AU1200
-/* EHCI (USB high speed host controller) */
-static struct resource au1xxx_usb_ehci_resources[] = {
- [0] = {
- .start = USB_EHCI_BASE,
- .end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_USB_INT,
- .end = AU1200_USB_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1xxx_usb_ehci_device = {
- .name = "au1xxx-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
- .resource = au1xxx_usb_ehci_resources,
-};
-
-/* Au1200 UDC (USB gadget controller) */
-static struct resource au1xxx_usb_gdt_resources[] = {
- [0] = {
- .start = USB_UDC_BASE,
- .end = USB_UDC_BASE + USB_UDC_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_USB_INT,
- .end = AU1200_USB_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 udc_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1xxx_usb_gdt_device = {
- .name = "au1xxx-udc",
- .id = 0,
- .dev = {
- .dma_mask = &udc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
- .resource = au1xxx_usb_gdt_resources,
-};
-
-/* Au1200 UOC (USB OTG controller) */
-static struct resource au1xxx_usb_otg_resources[] = {
- [0] = {
- .start = USB_UOC_BASE,
- .end = USB_UOC_BASE + USB_UOC_LEN - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_USB_INT,
- .end = AU1200_USB_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 uoc_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1xxx_usb_otg_device = {
- .name = "au1xxx-uoc",
- .id = 0,
- .dev = {
- .dma_mask = &uoc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
- .resource = au1xxx_usb_otg_resources,
-};
static struct resource au1200_lcd_resources[] = {
[0] = {
@@ -534,14 +504,10 @@ static void __init alchemy_setup_macs(int ctype)
}
static struct platform_device *au1xxx_platform_devices[] __initdata = {
- &au1xxx_usb_ohci_device,
#ifdef CONFIG_FB_AU1100
&au1100_lcd_device,
#endif
#ifdef CONFIG_SOC_AU1200
- &au1xxx_usb_ehci_device,
- &au1xxx_usb_gdt_device,
- &au1xxx_usb_otg_device,
&au1200_lcd_device,
&au1200_mmc0_device,
#ifndef CONFIG_MIPS_DB1200
@@ -559,6 +525,7 @@ static int __init au1xxx_platform_init(void)
alchemy_setup_uarts(ctype);
alchemy_setup_macs(ctype);
+ alchemy_setup_usb(ctype);
err = platform_add_devices(au1xxx_platform_devices,
ARRAY_SIZE(au1xxx_platform_devices));
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 73e0d79..86d39c3 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -833,56 +833,6 @@ enum soc_au1200_ints {
#endif
-
-
-/* Au1000 */
-#ifdef CONFIG_SOC_AU1000
-
-#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
-#define USB_HOST_CONFIG 0xB017FFFC
-#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
-#endif /* CONFIG_SOC_AU1000 */
-
-/* Au1500 */
-#ifdef CONFIG_SOC_AU1500
-
-#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
-#define USB_HOST_CONFIG 0xB017fffc
-#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
-#endif /* CONFIG_SOC_AU1500 */
-
-/* Au1100 */
-#ifdef CONFIG_SOC_AU1100
-
-#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
-#define USB_HOST_CONFIG 0xB017FFFC
-#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
-#endif /* CONFIG_SOC_AU1100 */
-
-#ifdef CONFIG_SOC_AU1550
-
-#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
-#define USB_OHCI_LEN 0x00060000
-#define USB_HOST_CONFIG 0xB4027ffc
-#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
-#endif /* CONFIG_SOC_AU1550 */
-
-
-#ifdef CONFIG_SOC_AU1200
-
-#define USB_UOC_BASE 0x14020020
-#define USB_UOC_LEN 0x20
-#define USB_OHCI_BASE 0x14020100
-#define USB_OHCI_LEN 0x100
-#define USB_EHCI_BASE 0x14020200
-#define USB_EHCI_LEN 0x100
-#define USB_UDC_BASE 0x14022000
-#define USB_UDC_LEN 0x2000
-
-#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
-
-#endif /* CONFIG_SOC_AU1200 */
-
/* Programmable Counters 0 and 1 */
#define SYS_BASE 0xB1900000
#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
@@ -953,11 +903,6 @@ enum soc_au1200_ints {
# define I2S_CONTROL_D (1 << 1)
# define I2S_CONTROL_CE (1 << 0)
-/* USB Host Controller */
-#ifndef USB_OHCI_LEN
-#define USB_OHCI_LEN 0x00100000
-#endif
-
/* Ethernet Controllers */
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 3/8] MIPS: Alchemy: more base address cleanup
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
2011-08-12 9:39 ` Manuel Lauss
2011-08-12 9:39 ` [PATCH 2/8] MIPS: Alchemy: rewrite USB platform setup Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-15 13:24 ` Ralf Baechle
2011-08-12 9:39 ` [PATCH 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep Manuel Lauss
` (4 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss
remove all redundant peripheral base address defines, fix
all affected boards and drivers.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
arch/mips/alchemy/common/platform.c | 12 ++--
arch/mips/alchemy/devboards/db1200/platform.c | 52 ++++++-------
arch/mips/alchemy/devboards/db1x00/platform.c | 40 ++++-----
arch/mips/alchemy/devboards/pb1100/platform.c | 20 ++---
arch/mips/alchemy/devboards/pb1200/platform.c | 42 +++++-----
arch/mips/alchemy/devboards/pb1500/platform.c | 22 +++---
arch/mips/alchemy/devboards/pb1550/platform.c | 40 ++++-----
arch/mips/alchemy/xxs1500/platform.c | 12 ++--
arch/mips/include/asm/mach-au1x00/au1000.h | 103 ++++++------------------
arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 ------
arch/mips/include/asm/mach-db1x00/db1x00.h | 8 +-
arch/mips/include/asm/mach-pb1x00/pb1200.h | 8 +-
arch/mips/include/asm/mach-pb1x00/pb1550.h | 8 +-
13 files changed, 146 insertions(+), 247 deletions(-)
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 910a3bd..bf1ac41 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -194,8 +194,8 @@ static void __init alchemy_setup_usb(int ctype)
#ifdef CONFIG_FB_AU1100
static struct resource au1100_lcd_resources[] = {
[0] = {
- .start = LCD_PHYS_ADDR,
- .end = LCD_PHYS_ADDR + 0x800 - 1,
+ .start = AU1100_LCD_PHYS_ADDR,
+ .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -223,8 +223,8 @@ static struct platform_device au1100_lcd_device = {
static struct resource au1200_lcd_resources[] = {
[0] = {
- .start = LCD_PHYS_ADDR,
- .end = LCD_PHYS_ADDR + 0x800 - 1,
+ .start = AU1200_LCD_PHYS_ADDR,
+ .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -328,8 +328,8 @@ static struct platform_device au1200_mmc1_device = {
#ifdef SMBUS_PSC_BASE
static struct resource pbdb_smbus_resources[] = {
{
- .start = CPHYSADDR(SMBUS_PSC_BASE),
- .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
+ .start = SMBUS_PSC_BASE,
+ .end = SMBUS_PSC_BASE + 0xfff,
.flags = IORESOURCE_MEM,
},
};
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index fbb5593..95c7327 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -343,8 +343,8 @@ struct au1xmmc_platform_data au1xmmc_platdata[] = {
static struct resource au1200_psc0_res[] = {
[0] = {
- .start = PSC0_PHYS_ADDR,
- .end = PSC0_PHYS_ADDR + 0x000fffff,
+ .start = AU1550_PSC0_PHYS_ADDR,
+ .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -401,8 +401,8 @@ static struct platform_device db1200_spi_dev = {
static struct resource au1200_psc1_res[] = {
[0] = {
- .start = PSC1_PHYS_ADDR,
- .end = PSC1_PHYS_ADDR + 0x000fffff,
+ .start = AU1550_PSC1_PHYS_ADDR,
+ .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -510,32 +510,28 @@ static int __init db1200_dev_init(void)
/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
__raw_writel(PSC_SEL_CLK_SERCLK,
- (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+ (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
wmb();
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- DB1200_PC0_INT,
- DB1200_PC0_INSERT_INT,
- /*DB1200_PC0_STSCHG_INT*/0,
- DB1200_PC0_EJECT_INT,
- 0);
-
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x004000000,
- PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x004000000,
- PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
- DB1200_PC1_INT,
- DB1200_PC1_INSERT_INT,
- /*DB1200_PC1_STSCHG_INT*/0,
- DB1200_PC1_EJECT_INT,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
+ /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
+
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
+ DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
+ /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
db1x_register_norflash(64 << 20, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 978d5ab..ef8017f 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -88,29 +88,25 @@
static int __init db1xxx_dev_init(void)
{
#ifdef DB1XXX_HAS_PCMCIA
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- DB1XXX_PCMCIA_CARD0,
- DB1XXX_PCMCIA_CD0,
- /*DB1XXX_PCMCIA_STSCHG0*/0,
- 0,
- 0);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
+ /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x004000000,
- PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x004000000,
- PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
- DB1XXX_PCMCIA_CARD1,
- DB1XXX_PCMCIA_CD1,
- /*DB1XXX_PCMCIA_STSCHG1*/0,
- 0,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
+ DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
+ /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
#endif
db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
return 0;
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
index 2c8dc29..8a4e733 100644
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -30,17 +30,15 @@ static int __init pb1100_dev_init(void)
int swapped;
/* PCMCIA. single socket, identical to Pb1500 */
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- AU1100_GPIO11_INT, /* card */
- AU1100_GPIO9_INT, /* insert */
- /*AU1100_GPIO10_INT*/0, /* stschg */
- 0, /* eject */
- 0); /* id */
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
+ /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 3ef2dce..c52809d 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -170,29 +170,25 @@ static int __init board_register_devices(void)
{
int swapped;
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- PB1200_PC0_INT,
- PB1200_PC0_INSERT_INT,
- /*PB1200_PC0_STSCHG_INT*/0,
- PB1200_PC0_EJECT_INT,
- 0);
-
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x008000000,
- PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x008000000,
- PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
- PB1200_PC1_INT,
- PB1200_PC1_INSERT_INT,
- /*PB1200_PC1_STSCHG_INT*/0,
- PB1200_PC1_EJECT_INT,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
+ /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
+
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
+ PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
+ /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index d443bc7..42b0e6b 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -28,18 +28,16 @@ static int __init pb1500_dev_init(void)
{
int swapped;
- /* PCMCIA. single socket, identical to Pb1500 */
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- AU1500_GPIO11_INT, /* card */
- AU1500_GPIO9_INT, /* insert */
- /*AU1500_GPIO10_INT*/0, /* stschg */
- 0, /* eject */
- 0); /* id */
+ /* PCMCIA. single socket, identical to Pb1100 */
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
+ /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index d7150d0..87c79b7 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -37,29 +37,23 @@ static int __init pb1550_dev_init(void)
* drivers are used to shared irqs and b) statuschange isn't really use-
* ful anyway.
*/
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
- PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_MEM_PHYS_ADDR,
- PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
- PCMCIA_IO_PHYS_ADDR,
- PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
- AU1550_GPIO201_205_INT,
- AU1550_GPIO0_INT,
- 0,
- 0,
- 0);
-
- db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
- PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_MEM_PHYS_ADDR + 0x008000000,
- PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
- PCMCIA_IO_PHYS_ADDR + 0x008000000,
- PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
- AU1550_GPIO201_205_INT,
- AU1550_GPIO1_INT,
- 0,
- 0,
- 1);
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
+ AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
+
+ db1x_register_pcmcia_socket(
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
+ AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
+ AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
index e87c45c..06a3a45 100644
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = {
{
.name = "pcmcia-io",
.flags = IORESOURCE_MEM,
- .start = PCMCIA_IO_PHYS_ADDR,
- .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
+ .start = AU1000_PCMCIA_IO_PHYS_ADDR,
+ .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
},
{
.name = "pcmcia-attr",
.flags = IORESOURCE_MEM,
- .start = PCMCIA_ATTR_PHYS_ADDR,
- .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+ .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
+ .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
},
{
.name = "pcmcia-mem",
.flags = IORESOURCE_MEM,
- .start = PCMCIA_MEM_PHYS_ADDR,
- .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+ .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
+ .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
},
};
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 86d39c3..bcf3d1e 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -698,114 +698,61 @@ enum soc_au1200_ints {
#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
+#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
+#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */
#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
+#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
+#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
+#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
+#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
+#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
+#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
+#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
+#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
+#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
+#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */
+#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
+#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
+#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
+#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
+#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
+#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */
+#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
+#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
+#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
+#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
+#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */
+#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */
+#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
-#ifdef CONFIG_SOC_AU1000
-#define MEM_PHYS_ADDR 0x14000000
-#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define IRDA_PHYS_ADDR 0x10300000
-#define SSI0_PHYS_ADDR 0x11600000
-#define SSI1_PHYS_ADDR 0x11680000
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1500
-#define MEM_PHYS_ADDR 0x14000000
-#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define PCI_PHYS_ADDR 0x14005000
-#define PCI_MEM_PHYS_ADDR 0x400000000ULL
-#define PCI_IO_PHYS_ADDR 0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1100
-#define MEM_PHYS_ADDR 0x14000000
-#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define IRDA_PHYS_ADDR 0x10300000
-#define SSI0_PHYS_ADDR 0x11600000
-#define SSI1_PHYS_ADDR 0x11680000
-#define LCD_PHYS_ADDR 0x15000000
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1550
-#define MEM_PHYS_ADDR 0x14000000
-#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define PCI_PHYS_ADDR 0x14005000
-#define PE_PHYS_ADDR 0x14008000
-#define PSC0_PHYS_ADDR 0x11A00000
-#define PSC1_PHYS_ADDR 0x11B00000
-#define PSC2_PHYS_ADDR 0x10A00000
-#define PSC3_PHYS_ADDR 0x10B00000
-#define PCI_MEM_PHYS_ADDR 0x400000000ULL
-#define PCI_IO_PHYS_ADDR 0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1200
-#define MEM_PHYS_ADDR 0x14000000
-#define STATIC_MEM_PHYS_ADDR 0x14001000
-#define AES_PHYS_ADDR 0x10300000
-#define CIM_PHYS_ADDR 0x14004000
-#define PSC0_PHYS_ADDR 0x11A00000
-#define PSC1_PHYS_ADDR 0x11B00000
-#define LCD_PHYS_ADDR 0x15000000
-#define SWCNT_PHYS_ADDR 0x1110010C
-#define MAEFE_PHYS_ADDR 0x14012000
-#define MAEBE_PHYS_ADDR 0x14010000
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
-#endif
-
/* Static Bus Controller */
#define MEM_STCFG0 0xB4001000
#define MEM_STTIME0 0xB4001004
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f1..8e2fa67 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -33,19 +33,6 @@
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
-/* The PSC base addresses. */
-#ifdef CONFIG_SOC_AU1550
-#define PSC0_BASE_ADDR 0xb1a00000
-#define PSC1_BASE_ADDR 0xb1b00000
-#define PSC2_BASE_ADDR 0xb0a00000
-#define PSC3_BASE_ADDR 0xb0b00000
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#define PSC0_BASE_ADDR 0xb1a00000
-#define PSC1_BASE_ADDR 0xb1b00000
-#endif
-
/*
* The PSC select and control registers are common to all protocols.
*/
@@ -80,19 +67,6 @@
#define PSC_AC97GPO_OFFSET 0x00000028
#define PSC_AC97GPI_OFFSET 0x0000002c
-#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
-#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
-#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
-#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
-#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
-#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
-#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
-#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
-#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
-#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
-#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
-#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
-
/* AC97 Config Register. */
#define PSC_AC97CFG_RT_MASK (3 << 30)
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index a919dac..115cc7c 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -36,10 +36,10 @@
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define AC97_PSC_BASE PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE PSC2_BASE_ADDR
-#define I2S_PSC_BASE PSC3_BASE_ADDR
+#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
+#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
+#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
+#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
#define NAND_PHYS_ADDR 0x20000000
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index fce4332..0ecff1c 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -37,14 +37,14 @@
* SPI and SMB are muxed on the Pb1200 board.
* Refer to board documentation.
*/
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE PSC0_BASE_ADDR
+#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
+#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
/*
* AC97 and I2S are muxed on the Pb1200 board.
* Refer to board documentation.
*/
-#define AC97_PSC_BASE PSC1_BASE_ADDR
-#define I2S_PSC_BASE PSC1_BASE_ADDR
+#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
+#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
#define BCSR_SYSTEM_VDDI 0x001F
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index f835c88..0b0f462 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -35,10 +35,10 @@
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define AC97_PSC_BASE PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE PSC2_BASE_ADDR
-#define I2S_PSC_BASE PSC3_BASE_ADDR
+#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
+#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
+#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
+#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
/*
* Timing values as described in databook, * ns value stripped of
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
` (2 preceding siblings ...)
2011-08-12 9:39 ` [PATCH 3/8] MIPS: Alchemy: more base address cleanup Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-12 9:39 ` [PATCH 5/8] MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines Manuel Lauss
` (3 subsequent siblings)
7 siblings, 0 replies; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss, linux-ide
au1xxx-ide uses defines from the pb1200/db1200 headers:
get DBDMA ID through platform resource information,
hardcode register spacing. The only 2 users of this driver (and
the only boards it can really work on realiably) use the same
register layout.
Cc: linux-ide@vger.kernel.org
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
I'd like for this to go through the MIPS tree, as other changes in it
depend on it.
arch/mips/alchemy/devboards/db1200/platform.c | 7 +++-
arch/mips/alchemy/devboards/pb1200/platform.c | 8 ++++-
arch/mips/include/asm/mach-au1x00/au1xxx_ide.h | 1 +
arch/mips/include/asm/mach-db1x00/db1200.h | 2 -
arch/mips/include/asm/mach-pb1x00/pb1200.h | 2 -
drivers/ide/au1xxx-ide.c | 44 ++++++++++++++----------
6 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 95c7327..6fd070d 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -213,7 +213,12 @@ static struct resource db1200_ide_res[] = {
.start = DB1200_IDE_INT,
.end = DB1200_IDE_INT,
.flags = IORESOURCE_IRQ,
- }
+ },
+ [2] = {
+ .start = DSCR_CMD0_DMA_REQ1,
+ .end = DSCR_CMD0_DMA_REQ1,
+ .flags = IORESOURCE_DMA,
+ },
};
static u64 ide_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index c52809d..6ac0494 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -26,6 +26,7 @@
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
@@ -115,7 +116,12 @@ static struct resource ide_resources[] = {
.start = IDE_INT,
.end = IDE_INT,
.flags = IORESOURCE_IRQ
- }
+ },
+ [2] = {
+ .start = DSCR_CMD0_DMA_REQ1,
+ .end = DSCR_CMD0_DMA_REQ1,
+ .flags = IORESOURCE_DMA,
+ },
};
static u64 ide_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
index 5656c72..e306384 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -58,6 +58,7 @@ typedef struct {
#endif
int irq;
u32 regbase;
+ int ddma_id;
} _auide_hwif;
/******************************************************************************/
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 3404248..7a39657 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -46,8 +46,6 @@
#define IDE_PHYS_ADDR 0x18800000
#define IDE_REG_SHIFT 5
-#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
-#define IDE_RQSIZE 128
#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index 0ecff1c..56865e9 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -76,8 +76,6 @@
#define IDE_REG_SHIFT 5
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
#define IDE_INT PB1200_IDE_INT
-#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
-#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x1C000000
diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c
index b26c234..c778373 100644
--- a/drivers/ide/au1xxx-ide.c
+++ b/drivers/ide/au1xxx-ide.c
@@ -43,6 +43,10 @@
#define DRV_NAME "au1200-ide"
#define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
+#ifndef IDE_REG_SHIFT
+#define IDE_REG_SHIFT 5
+#endif
+
/* enable the burstmode in the dbdma */
#define IDE_AU1XXX_BURSTMODE 1
@@ -317,10 +321,11 @@ static void auide_ddma_rx_callback(int irq, void *param)
}
#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
-static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
+static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize,
+ u32 devwidth, u32 flags, u32 regbase)
{
dev->dev_id = dev_id;
- dev->dev_physaddr = (u32)IDE_PHYS_ADDR;
+ dev->dev_physaddr = CPHYSADDR(regbase);
dev->dev_intlevel = 0;
dev->dev_intpolarity = 0;
dev->dev_tsize = tsize;
@@ -344,7 +349,7 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
dbdev_tab_t source_dev_tab, target_dev_tab;
u32 dev_id, tsize, devwidth, flags;
- dev_id = IDE_DDMA_REQ;
+ dev_id = hwif->ddma_id;
tsize = 8; /* 1 */
devwidth = 32; /* 16 */
@@ -356,20 +361,17 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
#endif
/* setup dev_tab for tx channel */
- auide_init_dbdma_dev( &source_dev_tab,
- dev_id,
- tsize, devwidth, DEV_FLAGS_OUT | flags);
+ auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth,
+ DEV_FLAGS_OUT | flags, auide->regbase);
auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
- auide_init_dbdma_dev( &source_dev_tab,
- dev_id,
- tsize, devwidth, DEV_FLAGS_IN | flags);
+ auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth,
+ DEV_FLAGS_IN | flags, auide->regbase);
auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
/* We also need to add a target device for the DMA */
- auide_init_dbdma_dev( &target_dev_tab,
- (u32)DSCR_CMD0_ALWAYS,
- tsize, devwidth, DEV_FLAGS_ANYUSE);
+ auide_init_dbdma_dev(&target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize,
+ devwidth, DEV_FLAGS_ANYUSE, auide->regbase);
auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
/* Get a channel for TX */
@@ -411,14 +413,12 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
#endif
/* setup dev_tab for tx channel */
- auide_init_dbdma_dev( &source_dev_tab,
- (u32)DSCR_CMD0_ALWAYS,
- 8, 32, DEV_FLAGS_OUT | flags);
+ auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32,
+ DEV_FLAGS_OUT | flags, auide->regbase);
auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
- auide_init_dbdma_dev( &source_dev_tab,
- (u32)DSCR_CMD0_ALWAYS,
- 8, 32, DEV_FLAGS_IN | flags);
+ auide_init_dbdma_dev(&source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32,
+ DEV_FLAGS_IN | flags, auide->regbase);
auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
/* Get a channel for TX */
@@ -540,6 +540,14 @@ static int au_ide_probe(struct platform_device *dev)
goto out;
}
+ res = platform_get_resource(dev, IORESOURCE_DMA, 0);
+ if (!res) {
+ pr_debug("%s: no DDMA ID resource\n", DRV_NAME);
+ ret = -ENODEV;
+ goto out;
+ }
+ ahwif->ddma_id = res->start;
+
memset(&hw, 0, sizeof(hw));
auide_setup_ports(&hw, ahwif);
hw.irq = ahwif->irq;
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 5/8] MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
` (3 preceding siblings ...)
2011-08-12 9:39 ` [PATCH 4/8] MIPS: au1xxx: au1xxx-ide: remove pb1200/db1200 header dep Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-18 19:12 ` Ralf Baechle
2011-08-12 9:39 ` [PATCH 6/8] MIPS: Alchemy: kill au1xxx.h header Manuel Lauss
` (2 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss
This patch gets rid of all CONFIG_SOC_AU1XXX defines in
DMA/DBDMA-related code.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
arch/mips/alchemy/common/dbdma.c | 203 ++++++++++------------
arch/mips/alchemy/common/dma.c | 60 +++----
arch/mips/alchemy/common/platform.c | 16 +-
arch/mips/alchemy/devboards/db1200/platform.c | 20 +-
arch/mips/alchemy/devboards/pb1200/platform.c | 4 +-
arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 114 ++++++-------
arch/mips/include/asm/mach-db1x00/db1x00.h | 8 +-
arch/mips/include/asm/mach-pb1x00/pb1200.h | 8 +-
arch/mips/include/asm/mach-pb1x00/pb1550.h | 8 +-
9 files changed, 206 insertions(+), 235 deletions(-)
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 3a5abb5..0e63ee4 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -40,8 +40,6 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-
/*
* The Descriptor Based DMA supports up to 16 channels.
*
@@ -62,120 +60,96 @@ static dbdma_global_t *dbdma_gptr =
(dbdma_global_t *)KSEG1ADDR(AU1550_DBDMA_CONF_PHYS_ADDR);
static int dbdma_initialized;
-static dbdev_tab_t dbdev_tab[] = {
-#ifdef CONFIG_SOC_AU1550
+static dbdev_tab_t *dbdev_tab;
+
+static dbdev_tab_t au1550_dbdev_tab[] __initdata = {
/* UARTS */
- { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
- { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
- { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
- { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
+ { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
+ { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
+ { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
+ { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
/* EXT DMA */
- { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
/* USB DEV */
- { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
- { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
- { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
- { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
- { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
- { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
-
- /* PSC 0 */
- { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
-
- /* PSC 1 */
- { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
-
- /* PSC 2 */
- { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
- { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
-
- /* PSC 3 */
- { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
- { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
-
- { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
- { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
+ { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
+ { AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
+
+ /* PSCs */
+ { AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
+ { AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
+
+ { AU1550_DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
+ { AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
/* MAC 0 */
- { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
/* MAC 1 */
- { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-
-#endif /* CONFIG_SOC_AU1550 */
+ { AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
-#ifdef CONFIG_SOC_AU1200
- { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
- { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
- { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
- { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
-
- { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+};
- { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
+ { AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
+ { AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
+ { AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
+ { AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
- { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
- { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
- { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
- { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
+ { AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
- { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
+ { AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
- { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
+ { AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
- { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
- { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
+ { AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
- { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
- { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
- { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
- { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
+ { AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
+ { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-#endif /* CONFIG_SOC_AU1200 */
+ { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
- { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
-
- /* Provide 16 user definable device types */
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
- { ~0, 0, 0, 0, 0, 0, 0 },
+ { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
};
-#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
-
+/* 32 predefined plus 32 custom */
+#define DBDEV_TAB_SIZE 64
static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
@@ -1028,38 +1002,43 @@ static struct syscore_ops alchemy_dbdma_syscore_ops = {
.resume = alchemy_dbdma_resume,
};
-static int __init au1xxx_dbdma_init(void)
+static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
{
- int irq_nr, ret;
+ int ret;
+
+ dbdev_tab = kzalloc(sizeof(dbdev_tab_t) * DBDEV_TAB_SIZE, GFP_KERNEL);
+ if (!dbdev_tab)
+ return -ENOMEM;
+
+ memcpy(dbdev_tab, idtable, 32 * sizeof(dbdev_tab_t));
+ for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
+ dbdev_tab[ret].dev_id = ~0;
dbdma_gptr->ddma_config = 0;
dbdma_gptr->ddma_throttle = 0;
dbdma_gptr->ddma_inten = 0xffff;
au_sync();
- switch (alchemy_get_cputype()) {
- case ALCHEMY_CPU_AU1550:
- irq_nr = AU1550_DDMA_INT;
- break;
- case ALCHEMY_CPU_AU1200:
- irq_nr = AU1200_DDMA_INT;
- break;
- default:
- return -ENODEV;
- }
-
- ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
- "Au1xxx dbdma", (void *)dbdma_gptr);
+ ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",
+ (void *)dbdma_gptr);
if (ret)
printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
else {
dbdma_initialized = 1;
- printk(KERN_INFO "Alchemy DBDMA initialized\n");
register_syscore_ops(&alchemy_dbdma_syscore_ops);
}
return ret;
}
-subsys_initcall(au1xxx_dbdma_init);
-#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
+static int __init alchemy_dbdma_init(void)
+{
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1550:
+ return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
+ case ALCHEMY_CPU_AU1200:
+ return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
+ }
+ return 0;
+}
+subsys_initcall(alchemy_dbdma_init);
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 6652a23..9b624e2 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -40,8 +40,6 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
- defined(CONFIG_SOC_AU1100)
/*
* A note on resource allocation:
*
@@ -170,13 +168,13 @@ int request_au1000_dma(int dev_id, const char *dev_str,
const struct dma_dev *dev;
int i, ret;
-#if defined(CONFIG_SOC_AU1100)
- if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
- return -EINVAL;
-#else
- if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
- return -EINVAL;
-#endif
+ if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
+ if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
+ return -EINVAL;
+ } else {
+ if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
+ return -EINVAL;
+ }
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
if (au1000_dma_table[i].dev_id < 0)
@@ -239,30 +237,28 @@ EXPORT_SYMBOL(free_au1000_dma);
static int __init au1000_dma_init(void)
{
- int base, i;
-
- switch (alchemy_get_cputype()) {
- case ALCHEMY_CPU_AU1000:
- base = AU1000_DMA_INT_BASE;
- break;
- case ALCHEMY_CPU_AU1500:
- base = AU1500_DMA_INT_BASE;
- break;
- case ALCHEMY_CPU_AU1100:
- base = AU1100_DMA_INT_BASE;
- break;
- default:
- goto out;
- }
-
- for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
- au1000_dma_table[i].irq = base + i;
-
- printk(KERN_INFO "Alchemy DMA initialized\n");
+ int base, i;
+
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1000:
+ base = AU1000_DMA_INT_BASE;
+ break;
+ case ALCHEMY_CPU_AU1500:
+ base = AU1500_DMA_INT_BASE;
+ break;
+ case ALCHEMY_CPU_AU1100:
+ base = AU1100_DMA_INT_BASE;
+ break;
+ default:
+ goto out;
+ }
+
+ for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
+ au1000_dma_table[i].irq = base + i;
+
+ printk(KERN_INFO "Alchemy DMA initialized\n");
out:
- return 0;
+ return 0;
}
arch_initcall(au1000_dma_init);
-
-#endif /* AU1000 AU1500 AU1100 */
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index bf1ac41..7eca306 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -263,13 +263,13 @@ static struct resource au1200_mmc0_resources[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_SDMS_TX0,
- .end = DSCR_CMD0_SDMS_TX0,
+ .start = AU1200_DSCR_CMD0_SDMS_TX0,
+ .end = AU1200_DSCR_CMD0_SDMS_TX0,
.flags = IORESOURCE_DMA,
},
[3] = {
- .start = DSCR_CMD0_SDMS_RX0,
- .end = DSCR_CMD0_SDMS_RX0,
+ .start = AU1200_DSCR_CMD0_SDMS_RX0,
+ .end = AU1200_DSCR_CMD0_SDMS_RX0,
.flags = IORESOURCE_DMA,
}
};
@@ -299,13 +299,13 @@ static struct resource au1200_mmc1_resources[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_SDMS_TX1,
- .end = DSCR_CMD0_SDMS_TX1,
+ .start = AU1200_DSCR_CMD0_SDMS_TX1,
+ .end = AU1200_DSCR_CMD0_SDMS_TX1,
.flags = IORESOURCE_DMA,
},
[3] = {
- .start = DSCR_CMD0_SDMS_RX1,
- .end = DSCR_CMD0_SDMS_RX1,
+ .start = AU1200_DSCR_CMD0_SDMS_RX1,
+ .end = AU1200_DSCR_CMD0_SDMS_RX1,
.flags = IORESOURCE_DMA,
}
};
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 6fd070d..1bc16f0 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -215,8 +215,8 @@ static struct resource db1200_ide_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_DMA_REQ1,
- .end = DSCR_CMD0_DMA_REQ1,
+ .start = AU1200_DSCR_CMD0_DMA_REQ1,
+ .end = AU1200_DSCR_CMD0_DMA_REQ1,
.flags = IORESOURCE_DMA,
},
};
@@ -358,13 +358,13 @@ static struct resource au1200_psc0_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_PSC0_TX,
- .end = DSCR_CMD0_PSC0_TX,
+ .start = AU1200_DSCR_CMD0_PSC0_TX,
+ .end = AU1200_DSCR_CMD0_PSC0_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
- .start = DSCR_CMD0_PSC0_RX,
- .end = DSCR_CMD0_PSC0_RX,
+ .start = AU1200_DSCR_CMD0_PSC0_RX,
+ .end = AU1200_DSCR_CMD0_PSC0_RX,
.flags = IORESOURCE_DMA,
},
};
@@ -416,13 +416,13 @@ static struct resource au1200_psc1_res[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
- .start = DSCR_CMD0_PSC1_TX,
- .end = DSCR_CMD0_PSC1_TX,
+ .start = AU1200_DSCR_CMD0_PSC1_TX,
+ .end = AU1200_DSCR_CMD0_PSC1_TX,
.flags = IORESOURCE_DMA,
},
[3] = {
- .start = DSCR_CMD0_PSC1_RX,
- .end = DSCR_CMD0_PSC1_RX,
+ .start = AU1200_DSCR_CMD0_PSC1_RX,
+ .end = AU1200_DSCR_CMD0_PSC1_RX,
.flags = IORESOURCE_DMA,
},
};
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 6ac0494..7de4f88 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -118,8 +118,8 @@ static struct resource ide_resources[] = {
.flags = IORESOURCE_IRQ
},
[2] = {
- .start = DSCR_CMD0_DMA_REQ1,
- .end = DSCR_CMD0_DMA_REQ1,
+ .start = AU1200_DSCR_CMD0_DMA_REQ1,
+ .end = AU1200_DSCR_CMD0_DMA_REQ1,
.flags = IORESOURCE_DMA,
},
};
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 2fdacfe..323ce2d 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc {
#define SW_STATUS_INUSE (1 << 0)
/* Command 0 device IDs. */
-#ifdef CONFIG_SOC_AU1550
-#define DSCR_CMD0_UART0_TX 0
-#define DSCR_CMD0_UART0_RX 1
-#define DSCR_CMD0_UART3_TX 2
-#define DSCR_CMD0_UART3_RX 3
-#define DSCR_CMD0_DMA_REQ0 4
-#define DSCR_CMD0_DMA_REQ1 5
-#define DSCR_CMD0_DMA_REQ2 6
-#define DSCR_CMD0_DMA_REQ3 7
-#define DSCR_CMD0_USBDEV_RX0 8
-#define DSCR_CMD0_USBDEV_TX0 9
-#define DSCR_CMD0_USBDEV_TX1 10
-#define DSCR_CMD0_USBDEV_TX2 11
-#define DSCR_CMD0_USBDEV_RX3 12
-#define DSCR_CMD0_USBDEV_RX4 13
-#define DSCR_CMD0_PSC0_TX 14
-#define DSCR_CMD0_PSC0_RX 15
-#define DSCR_CMD0_PSC1_TX 16
-#define DSCR_CMD0_PSC1_RX 17
-#define DSCR_CMD0_PSC2_TX 18
-#define DSCR_CMD0_PSC2_RX 19
-#define DSCR_CMD0_PSC3_TX 20
-#define DSCR_CMD0_PSC3_RX 21
-#define DSCR_CMD0_PCI_WRITE 22
-#define DSCR_CMD0_NAND_FLASH 23
-#define DSCR_CMD0_MAC0_RX 24
-#define DSCR_CMD0_MAC0_TX 25
-#define DSCR_CMD0_MAC1_RX 26
-#define DSCR_CMD0_MAC1_TX 27
-#endif /* CONFIG_SOC_AU1550 */
-
-#ifdef CONFIG_SOC_AU1200
-#define DSCR_CMD0_UART0_TX 0
-#define DSCR_CMD0_UART0_RX 1
-#define DSCR_CMD0_UART1_TX 2
-#define DSCR_CMD0_UART1_RX 3
-#define DSCR_CMD0_DMA_REQ0 4
-#define DSCR_CMD0_DMA_REQ1 5
-#define DSCR_CMD0_MAE_BE 6
-#define DSCR_CMD0_MAE_FE 7
-#define DSCR_CMD0_SDMS_TX0 8
-#define DSCR_CMD0_SDMS_RX0 9
-#define DSCR_CMD0_SDMS_TX1 10
-#define DSCR_CMD0_SDMS_RX1 11
-#define DSCR_CMD0_AES_TX 13
-#define DSCR_CMD0_AES_RX 12
-#define DSCR_CMD0_PSC0_TX 14
-#define DSCR_CMD0_PSC0_RX 15
-#define DSCR_CMD0_PSC1_TX 16
-#define DSCR_CMD0_PSC1_RX 17
-#define DSCR_CMD0_CIM_RXA 18
-#define DSCR_CMD0_CIM_RXB 19
-#define DSCR_CMD0_CIM_RXC 20
-#define DSCR_CMD0_MAE_BOTH 21
-#define DSCR_CMD0_LCD 22
-#define DSCR_CMD0_NAND_FLASH 23
-#define DSCR_CMD0_PSC0_SYNC 24
-#define DSCR_CMD0_PSC1_SYNC 25
-#define DSCR_CMD0_CIM_SYNC 26
-#endif /* CONFIG_SOC_AU1200 */
+#define AU1550_DSCR_CMD0_UART0_TX 0
+#define AU1550_DSCR_CMD0_UART0_RX 1
+#define AU1550_DSCR_CMD0_UART3_TX 2
+#define AU1550_DSCR_CMD0_UART3_RX 3
+#define AU1550_DSCR_CMD0_DMA_REQ0 4
+#define AU1550_DSCR_CMD0_DMA_REQ1 5
+#define AU1550_DSCR_CMD0_DMA_REQ2 6
+#define AU1550_DSCR_CMD0_DMA_REQ3 7
+#define AU1550_DSCR_CMD0_USBDEV_RX0 8
+#define AU1550_DSCR_CMD0_USBDEV_TX0 9
+#define AU1550_DSCR_CMD0_USBDEV_TX1 10
+#define AU1550_DSCR_CMD0_USBDEV_TX2 11
+#define AU1550_DSCR_CMD0_USBDEV_RX3 12
+#define AU1550_DSCR_CMD0_USBDEV_RX4 13
+#define AU1550_DSCR_CMD0_PSC0_TX 14
+#define AU1550_DSCR_CMD0_PSC0_RX 15
+#define AU1550_DSCR_CMD0_PSC1_TX 16
+#define AU1550_DSCR_CMD0_PSC1_RX 17
+#define AU1550_DSCR_CMD0_PSC2_TX 18
+#define AU1550_DSCR_CMD0_PSC2_RX 19
+#define AU1550_DSCR_CMD0_PSC3_TX 20
+#define AU1550_DSCR_CMD0_PSC3_RX 21
+#define AU1550_DSCR_CMD0_PCI_WRITE 22
+#define AU1550_DSCR_CMD0_NAND_FLASH 23
+#define AU1550_DSCR_CMD0_MAC0_RX 24
+#define AU1550_DSCR_CMD0_MAC0_TX 25
+#define AU1550_DSCR_CMD0_MAC1_RX 26
+#define AU1550_DSCR_CMD0_MAC1_TX 27
+
+#define AU1200_DSCR_CMD0_UART0_TX 0
+#define AU1200_DSCR_CMD0_UART0_RX 1
+#define AU1200_DSCR_CMD0_UART1_TX 2
+#define AU1200_DSCR_CMD0_UART1_RX 3
+#define AU1200_DSCR_CMD0_DMA_REQ0 4
+#define AU1200_DSCR_CMD0_DMA_REQ1 5
+#define AU1200_DSCR_CMD0_MAE_BE 6
+#define AU1200_DSCR_CMD0_MAE_FE 7
+#define AU1200_DSCR_CMD0_SDMS_TX0 8
+#define AU1200_DSCR_CMD0_SDMS_RX0 9
+#define AU1200_DSCR_CMD0_SDMS_TX1 10
+#define AU1200_DSCR_CMD0_SDMS_RX1 11
+#define AU1200_DSCR_CMD0_AES_TX 13
+#define AU1200_DSCR_CMD0_AES_RX 12
+#define AU1200_DSCR_CMD0_PSC0_TX 14
+#define AU1200_DSCR_CMD0_PSC0_RX 15
+#define AU1200_DSCR_CMD0_PSC1_TX 16
+#define AU1200_DSCR_CMD0_PSC1_RX 17
+#define AU1200_DSCR_CMD0_CIM_RXA 18
+#define AU1200_DSCR_CMD0_CIM_RXB 19
+#define AU1200_DSCR_CMD0_CIM_RXC 20
+#define AU1200_DSCR_CMD0_MAE_BOTH 21
+#define AU1200_DSCR_CMD0_LCD 22
+#define AU1200_DSCR_CMD0_NAND_FLASH 23
+#define AU1200_DSCR_CMD0_PSC0_SYNC 24
+#define AU1200_DSCR_CMD0_PSC1_SYNC 25
+#define AU1200_DSCR_CMD0_CIM_SYNC 26
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index 115cc7c..a5affb0 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -31,10 +31,10 @@
#ifdef CONFIG_MIPS_DB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index 56865e9..374416a 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -28,10 +28,10 @@
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
/*
* SPI and SMB are muxed on the Pb1200 board.
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 0b0f462..443b88a 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -30,10 +30,10 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 6/8] MIPS: Alchemy: kill au1xxx.h header
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
` (4 preceding siblings ...)
2011-08-12 9:39 ` [PATCH 5/8] MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-18 19:13 ` Ralf Baechle
2011-08-12 9:39 ` [PATCH 7/8] MIPS: Alchemy: redo PCI as platform driver Manuel Lauss
2011-08-12 9:39 ` [PATCH 8/8] MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines Manuel Lauss
7 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss
No longer required
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
arch/mips/alchemy/common/platform.c | 2 +-
arch/mips/alchemy/devboards/db1x00/platform.c | 2 +-
arch/mips/alchemy/devboards/pb1200/platform.c | 3 +-
arch/mips/include/asm/mach-au1x00/au1xxx.h | 43 -------------------------
drivers/i2c/busses/i2c-au1550.c | 2 +-
drivers/ide/au1xxx-ide.c | 2 +-
drivers/mtd/nand/au1550nd.c | 6 +++-
7 files changed, 11 insertions(+), 49 deletions(-)
delete mode 100644 arch/mips/include/asm/mach-au1x00/au1xxx.h
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 7eca306..657ae27 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -18,7 +18,7 @@
#include <linux/serial_8250.h>
#include <linux/slab.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index ef8017f..70bcfb5 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -21,7 +21,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 7de4f88..d7915b0 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -24,10 +24,11 @@
#include <linux/platform_device.h>
#include <linux/smc91x.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1100_mmc.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-pb1x00/pb1200.h>
#include "../platform.h"
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h
deleted file mode 100644
index 1b36550..0000000
--- a/arch/mips/include/asm/mach-au1x00/au1xxx.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _AU1XXX_H_
-#define _AU1XXX_H_
-
-#include <asm/mach-au1x00/au1000.h>
-
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
- defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
-#include <asm/mach-db1x00/db1x00.h>
-
-#elif defined(CONFIG_MIPS_PB1550)
-#include <asm/mach-pb1x00/pb1550.h>
-
-#elif defined(CONFIG_MIPS_PB1200)
-#include <asm/mach-pb1x00/pb1200.h>
-
-#elif defined(CONFIG_MIPS_DB1200)
-#include <asm/mach-db1x00/db1200.h>
-
-#endif
-
-#endif /* _AU1XXX_H_ */
diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c
index 532828b..a714534 100644
--- a/drivers/i2c/busses/i2c-au1550.c
+++ b/drivers/i2c/busses/i2c-au1550.c
@@ -36,7 +36,7 @@
#include <linux/i2c.h>
#include <linux/slab.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
struct i2c_au1550_data {
diff --git a/drivers/ide/au1xxx-ide.c b/drivers/ide/au1xxx-ide.c
index c778373..259786c 100644
--- a/drivers/ide/au1xxx-ide.c
+++ b/drivers/ide/au1xxx-ide.c
@@ -36,7 +36,7 @@
#include <linux/ide.h>
#include <linux/scatterlist.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1xxx_ide.h>
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index e7767ee..fa5736b 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -19,7 +19,11 @@
#include <linux/mtd/partitions.h>
#include <asm/io.h>
-#include <asm/mach-au1x00/au1xxx.h>
+#ifdef CONFIG_MIPS_PB1550
+#include <asm/mach-pb1x00/pb1550.h>
+#elif defined(CONFIG_MIPS_DB1550)
+#include <asm/mach-db1x00/db1x00.h>
+#endif
#include <asm/mach-db1x00/bcsr.h>
/*
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 7/8] MIPS: Alchemy: redo PCI as platform driver
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
` (5 preceding siblings ...)
2011-08-12 9:39 ` [PATCH 6/8] MIPS: Alchemy: kill au1xxx.h header Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-15 13:25 ` Ralf Baechle
2011-08-12 9:39 ` [PATCH 8/8] MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines Manuel Lauss
7 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss
- Rewrite Alchemy PCI support as a platform driver.
- Fixup boards which have PCI.
Run-tested on DB1500 and DB1550.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
arch/mips/alchemy/common/Makefile | 2 -
arch/mips/alchemy/common/pci.c | 104 -----
arch/mips/alchemy/common/setup.c | 6 +-
arch/mips/alchemy/devboards/db1x00/board_setup.c | 24 -
arch/mips/alchemy/devboards/db1x00/platform.c | 123 +++++
arch/mips/alchemy/devboards/pb1500/board_setup.c | 33 +-
arch/mips/alchemy/devboards/pb1500/platform.c | 48 ++-
arch/mips/alchemy/devboards/pb1550/board_setup.c | 6 -
arch/mips/alchemy/devboards/pb1550/platform.c | 48 ++-
arch/mips/alchemy/gpr/board_setup.c | 12 -
arch/mips/alchemy/gpr/platform.c | 47 ++
arch/mips/alchemy/mtx-1/board_setup.c | 40 --
arch/mips/alchemy/mtx-1/platform.c | 62 +++
arch/mips/alchemy/xxs1500/board_setup.c | 8 -
arch/mips/include/asm/mach-au1x00/au1000.h | 142 ++++--
arch/mips/pci/Makefile | 3 +-
arch/mips/pci/fixup-au1000.c | 43 --
arch/mips/pci/ops-au1000.c | 308 -------------
arch/mips/pci/pci-alchemy.c | 516 ++++++++++++++++++++++
19 files changed, 950 insertions(+), 625 deletions(-)
delete mode 100644 arch/mips/alchemy/common/pci.c
delete mode 100644 arch/mips/pci/fixup-au1000.c
delete mode 100644 arch/mips/pci/ops-au1000.c
create mode 100644 arch/mips/pci/pci-alchemy.c
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 31728e0..3792739 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -14,5 +14,3 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
obj-$(CONFIG_GPIOLIB) += gpiolib.o
endif
-
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
deleted file mode 100644
index 7866cf5..0000000
--- a/arch/mips/alchemy/common/pci.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Alchemy/AMD Au1x00 PCI support.
- *
- * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * Support for all devices (greater than 16) added by David Gathright.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-/* TBD */
-static struct resource pci_io_resource = {
- .start = PCI_IO_START,
- .end = PCI_IO_END,
- .name = "PCI IO space",
- .flags = IORESOURCE_IO
-};
-
-static struct resource pci_mem_resource = {
- .start = PCI_MEM_START,
- .end = PCI_MEM_END,
- .name = "PCI memory space",
- .flags = IORESOURCE_MEM
-};
-
-extern struct pci_ops au1x_pci_ops;
-
-static struct pci_controller au1x_controller = {
- .pci_ops = &au1x_pci_ops,
- .io_resource = &pci_io_resource,
- .mem_resource = &pci_mem_resource,
-};
-
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-static unsigned long virt_io_addr;
-#endif
-
-static int __init au1x_pci_setup(void)
-{
- extern void au1x_pci_cfg_init(void);
-
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
- virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
- Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
-
- if (!virt_io_addr) {
- printk(KERN_ERR "Unable to ioremap pci space\n");
- return 1;
- }
- au1x_controller.io_map_base = virt_io_addr;
-
-#ifdef CONFIG_DMA_NONCOHERENT
- {
- /*
- * Set the NC bit in controller for Au1500 pre-AC silicon
- */
- u32 prid = read_c0_prid();
-
- if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
- au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
- Au1500_PCI_CFG);
- printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
- }
- }
-#endif
-
- set_io_port_base(virt_io_addr);
-#endif
-
- au1x_pci_cfg_init();
-
- register_pci_controller(&au1x_controller);
- return 0;
-}
-
-arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1b887c8..37ffd99 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -73,8 +73,8 @@ void __init plat_mem_setup(void)
/* This routine should be valid for all Au1x based boards */
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
- u32 start = (u32)Au1500_PCI_MEM_START;
- u32 end = (u32)Au1500_PCI_MEM_END;
+ unsigned long start = ALCHEMY_PCI_MEMWIN_START;
+ unsigned long end = ALCHEMY_PCI_MEMWIN_END;
/* Don't fixup 36-bit addresses */
if ((phys_addr >> 32) != 0)
@@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
/* Check for PCI memory window */
if (phys_addr >= start && (phys_addr + size - 1) <= end)
- return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
+ return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
/* default nop */
return phys_addr;
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 5c956fe..2b2178f 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -40,24 +40,6 @@
#include <prom.h>
-#ifdef CONFIG_MIPS_DB1500
-char irq_tab_alchemy[][5] __initdata = {
- [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
- [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
-};
-
-#endif
-
-
-#ifdef CONFIG_MIPS_DB1550
-char irq_tab_alchemy[][5] __initdata = {
- [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
- [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
- [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
-};
-#endif
-
-
#ifdef CONFIG_MIPS_BOSPORUS
char irq_tab_alchemy[][5] __initdata = {
[11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
@@ -91,12 +73,6 @@ const char *get_system_type(void)
#ifdef CONFIG_MIPS_MIRAGE
-char irq_tab_alchemy[][5] __initdata = {
- [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
- [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
- [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
-};
-
static void mirage_power_off(void)
{
alchemy_gpio_direction_output(210, 1);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 70bcfb5..990367f 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -25,6 +25,8 @@
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+struct pci_dev;
+
/* DB1xxx PCMCIA interrupt sources:
* CD0/1 GPIO0/3
* STSCHG0/1 GPIO1/4
@@ -85,6 +87,127 @@
#endif
#endif
+#ifdef CONFIG_PCI
+#ifdef CONFIG_MIPS_DB1500
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 12) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12)
+ return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_MIPS_DB1550
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 11) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 11)
+ return (pin == 1) ? AU1550_PCI_INTC : 0xff;
+ if (slot == 12) {
+ switch (pin) {
+ case 1: return AU1550_PCI_INTB;
+ case 2: return AU1550_PCI_INTC;
+ case 3: return AU1550_PCI_INTD;
+ case 4: return AU1550_PCI_INTA;
+ }
+ }
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1550_PCI_INTA;
+ case 2: return AU1550_PCI_INTB;
+ case 3: return AU1550_PCI_INTC;
+ case 4: return AU1550_PCI_INTD;
+ }
+ }
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_MIPS_BOSPORUS
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 11) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12)
+ return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+ if (slot == 11) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ default: return 0xff;
+ }
+ }
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_MIPS_MIRAGE
+static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 11) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 11)
+ return (pin == 1) ? AU1500_PCI_INTD : 0xff;
+ if (slot == 12)
+ return (pin == 3) ? AU1500_PCI_INTC : 0xff;
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ default: return 0xff;
+ }
+ }
+ return -1;
+}
+#endif
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct alchemy_pci_platdata db1xxx_pci_pd = {
+ .board_map_irq = db1xxx_map_pci_irq,
+};
+
+static struct platform_device db1xxx_pci_host_dev = {
+ .dev.platform_data = &db1xxx_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
+static int __init db15x0_pci_init(void)
+{
+ return platform_device_register(&db1xxx_pci_host_dev);
+}
+/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
+arch_initcall(db15x0_pci_init);
+#endif
+
static int __init db1xxx_dev_init(void)
{
#ifdef DB1XXX_HAS_PCMCIA
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 3b4fa32..37c1883 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -33,13 +33,6 @@
#include <prom.h>
-
-char irq_tab_alchemy[][5] __initdata = {
- [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
- [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
-};
-
-
const char *get_system_type(void)
{
return "Alchemy Pb1500";
@@ -101,20 +94,18 @@ void __init board_setup(void)
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
#ifdef CONFIG_PCI
- /* Setup PCI bus controller */
- au_writel(0, Au1500_PCI_CMEM);
- au_writel(0x00003fff, Au1500_CFG_BASE);
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
- au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
- au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
- au_writel(0x02a00356, Au1500_PCI_STATCMD);
- au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
- au_writel(0x00000008, Au1500_PCI_MBAR);
- au_sync();
+ {
+ void __iomem *base =
+ (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
+ /* Setup PCI bus controller */
+ __raw_writel(0x00003fff, base + PCI_REG_CMEM);
+ __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
+ __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
+ __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
+ __raw_writel(0x00003c04, base + PCI_REG_PARAM);
+ __raw_writel(0x00000008, base + PCI_REG_MBAR);
+ wmb();
+ }
#endif
/* Enable sys bus clock divider when IDLE state or no bus activity. */
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index 42b0e6b..9f0b5a0 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -19,11 +19,56 @@
*/
#include <linux/init.h>
+#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 12) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12)
+ return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct alchemy_pci_platdata pb1500_pci_pd = {
+ .board_map_irq = pb1500_map_pci_irq,
+ .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+ PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+ PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+ 0,
+#endif
+};
+
+static struct platform_device pb1500_pci_host = {
+ .dev.platform_data = &pb1500_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
static int __init pb1500_dev_init(void)
{
int swapped;
@@ -41,7 +86,8 @@ static int __init pb1500_dev_init(void)
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+ platform_device_register(&pb1500_pci_host);
return 0;
}
-device_initcall(pb1500_dev_init);
+arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b790213..0f62d1e 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -37,12 +37,6 @@
#include <prom.h>
-
-char irq_tab_alchemy[][5] __initdata = {
- [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
- [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
-};
-
const char *get_system_type(void)
{
return "Alchemy Pb1550";
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index 87c79b7..0c5711f 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -19,13 +19,56 @@
*/
#include <linux/init.h>
-
+#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-pb1x00/pb1550.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot < 12) || (slot > 13) || pin == 0)
+ return -1;
+ if (slot == 12) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTB;
+ case 2: return AU1500_PCI_INTC;
+ case 3: return AU1500_PCI_INTD;
+ case 4: return AU1500_PCI_INTA;
+ }
+ }
+ if (slot == 13) {
+ switch (pin) {
+ case 1: return AU1500_PCI_INTA;
+ case 2: return AU1500_PCI_INTB;
+ case 3: return AU1500_PCI_INTC;
+ case 4: return AU1500_PCI_INTD;
+ }
+ }
+ return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct alchemy_pci_platdata pb1550_pci_pd = {
+ .board_map_irq = pb1550_map_pci_irq,
+};
+
+static struct platform_device pb1550_pci_host = {
+ .dev.platform_data = &pb1550_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
static int __init pb1550_dev_init(void)
{
int swapped;
@@ -57,7 +100,8 @@ static int __init pb1550_dev_init(void)
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
+ platform_device_register(&pb1550_pci_host);
return 0;
}
-device_initcall(pb1550_dev_init);
+arch_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
index 5f8f069..dea45c7 100644
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -36,10 +36,6 @@
#include <prom.h>
-char irq_tab_alchemy[][5] __initdata = {
- [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
-};
-
static void gpr_reset(char *c)
{
/* switch System-LED to orange (red# and green# on) */
@@ -76,12 +72,4 @@ void __init board_setup(void)
/* Take away Reset of UMTS-card */
alchemy_gpio_direction_output(215, 1);
-
-#ifdef CONFIG_PCI
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
-#endif
}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
index 14b4662..982ce85 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = {
}
};
+
+
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ if ((slot == 0) && (pin == 1))
+ return AU1550_PCI_INTA;
+ else if ((slot == 0) && (pin == 2))
+ return AU1550_PCI_INTB;
+
+ return -1;
+}
+
+static struct alchemy_pci_platdata gpr_pci_pd = {
+ .board_map_irq = gpr_map_pci_irq,
+ .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+ PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+ PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+ 0,
+#endif
+};
+
+static struct platform_device gpr_pci_host_dev = {
+ .dev.platform_data = &gpr_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
static struct platform_device *gpr_devices[] __initdata = {
&gpr_wdt_device,
&gpr_mtd_device,
@@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = {
&gpr_led_devices,
};
+static int __init gpr_pci_init(void)
+{
+ return platform_device_register(&gpr_pci_host_dev);
+}
+/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
+arch_initcall(gpr_pci_init);
+
+
static int __init gpr_dev_init(void)
{
i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3ae984c..851a5ab 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -38,20 +38,6 @@
#include <prom.h>
-char irq_tab_alchemy[][5] __initdata = {
- [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
- [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
- [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
- [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
- [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
- [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
- [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
- [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
-};
-
-extern int (*board_pci_idsel)(unsigned int devsel, int assert);
-int mtx1_pci_idsel(unsigned int devsel, int assert);
-
static void mtx1_reset(char *c)
{
/* Jump to the reset vector */
@@ -74,15 +60,6 @@ void __init board_setup(void)
alchemy_gpio_direction_output(204, 0);
#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
-#ifdef CONFIG_PCI
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
- board_pci_idsel = mtx1_pci_idsel;
-#endif
-
/* Initialize sys_pinfunc */
au_writel(SYS_PF_NI2, SYS_PINFUNC);
@@ -104,23 +81,6 @@ void __init board_setup(void)
printk(KERN_INFO "4G Systems MTX-1 Board\n");
}
-int
-mtx1_pci_idsel(unsigned int devsel, int assert)
-{
- /* This function is only necessary to support a proprietary Cardbus
- * adapter on the mtx-1 "singleboard" variant. It triggers a custom
- * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
- */
- if (assert && devsel != 0)
- /* Suppress signal to Cardbus */
- alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
- else
- alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
-
- udelay(1);
- return 1;
-}
-
static int __init mtx1_init_irq(void)
{
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 55628e3..cc47b68 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = {
.resource = &mtx1_mtd_resource,
};
+static struct resource alchemy_pci_host_res[] = {
+ [0] = {
+ .start = AU1500_PCI_PHYS_ADDR,
+ .end = AU1500_PCI_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int mtx1_pci_idsel(unsigned int devsel, int assert)
+{
+ /* This function is only necessary to support a proprietary Cardbus
+ * adapter on the mtx-1 "singleboard" variant. It triggers a custom
+ * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
+ */
+ if (assert && devsel != 0)
+ /* Suppress signal to Cardbus */
+ alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
+ else
+ alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
+
+ udelay(1);
+ return 1;
+}
+
+static const char mtx1_irqtab[][5] = {
+ [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
+ [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
+ [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
+ [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
+ [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
+ [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
+ [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
+ [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
+};
+
+static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+ return mtx1_irqtab[slot][pin];
+}
+
+static struct alchemy_pci_platdata mtx1_pci_pd = {
+ .board_map_irq = mtx1_map_pci_irq,
+ .board_pci_idsel = mtx1_pci_idsel,
+ .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+ PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+ PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+ 0,
+#endif
+};
+
+static struct platform_device mtx1_pci_host = {
+ .dev.platform_data = &mtx1_pci_pd,
+ .name = "alchemy-pci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
+ .resource = alchemy_pci_host_res,
+};
+
+
static struct __initdata platform_device * mtx1_devs[] = {
+ &mtx1_pci_host,
&mtx1_gpio_leds,
&mtx1_wdt,
&mtx1_button,
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 81e57fa..3fa83f7 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -70,14 +70,6 @@ void __init board_setup(void)
/* Enable DTR (MCR bit 0) = USB power up */
__raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
wmb();
-
-#ifdef CONFIG_PCI
-#if defined(__MIPSEB__)
- au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
-#else
- au_writel(0xf, Au1500_PCI_CFG);
-#endif
-#endif
}
static int __init xxs1500_init_irq(void)
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index bcf3d1e..5da2fd7 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -254,6 +254,14 @@ enum alchemy_usb_block {
};
int alchemy_usb_control(int block, int enable);
+/* PCI controller platform data */
+struct alchemy_pci_platdata {
+ int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
+ int (*board_pci_idsel)(unsigned int devsel, int assert);
+ /* bits to set/clear in PCI_CONFIG register */
+ unsigned long pci_cfg_set;
+ unsigned long pci_cfg_clr;
+};
/* SOC Interrupt numbers */
@@ -1309,58 +1317,30 @@ enum soc_au1200_ints {
# define AC97C_RS (1 << 1)
# define AC97C_CE (1 << 0)
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
-#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
-# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
- (1 << 25) | (1 << 26) | (1 << 27))
-#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
-
-#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
-/*
- * All of our structures, like PCI resource, have 32-bit members.
- * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
- * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
- * addresses. For PCI I/O, it's simpler because we get to do the ioremap
- * ourselves and then adjust the device's resources.
+/* The PCI chip selects are outside the 32bit space, and since we can't
+ * just program the 36bit addresses into BARs, we have to take a chunk
+ * out of the 32bit space and reserve it for PCI. When these addresses
+ * are ioremap()ed, they'll be fixed up to the real 36bit address before
+ * being passed to the real ioremap function.
*/
-#define Au1500_EXT_CFG 0x600000000ULL
-#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
-#define Au1500_PCI_IO_START 0x500000000ULL
-#define Au1500_PCI_IO_END 0x5000FFFFFULL
-#define Au1500_PCI_MEM_START 0x440000000ULL
-#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
+#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
+#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
-#define PCI_IO_START 0x00001000
-#define PCI_IO_END 0x000FFFFF
-#define PCI_MEM_START 0x40000000
-#define PCI_MEM_END 0x4FFFFFFF
+/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
+ * adjust the device's resources.
+ */
+#define ALCHEMY_PCI_IOWIN_START 0x00001000
+#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
-#define PCI_FIRST_DEVFN (0 << 3)
-#define PCI_LAST_DEVFN (19 << 3)
+#ifdef CONFIG_PCI
#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xfffffffffULL
-#else /* Au1000 and Au1100 and Au1200 */
+#else
/* Don't allow any legacy ports probing */
#define IOPORT_RESOURCE_START 0x10000000
@@ -1368,13 +1348,77 @@ enum soc_au1200_ints {
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xfffffffffULL
-#define PCI_IO_START 0
-#define PCI_IO_END 0
-#define PCI_MEM_START 0
-#define PCI_MEM_END 0
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN 0
-
#endif
+/* PCI controller block register offsets */
+#define PCI_REG_CMEM 0x0000
+#define PCI_REG_CONFIG 0x0004
+#define PCI_REG_B2BMASK_CCH 0x0008
+#define PCI_REG_B2BBASE0_VID 0x000C
+#define PCI_REG_B2BBASE1_SID 0x0010
+#define PCI_REG_MWMASK_DEV 0x0014
+#define PCI_REG_MWBASE_REV_CCL 0x0018
+#define PCI_REG_ERR_ADDR 0x001C
+#define PCI_REG_SPEC_INTACK 0x0020
+#define PCI_REG_ID 0x0100
+#define PCI_REG_STATCMD 0x0104
+#define PCI_REG_CLASSREV 0x0108
+#define PCI_REG_PARAM 0x010C
+#define PCI_REG_MBAR 0x0110
+#define PCI_REG_TIMEOUT 0x0140
+
+/* PCI controller block register bits */
+#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
+#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
+#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
+#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
+#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
+#define PCI_CONFIG_EF (1 << 25) /* fatal error */
+#define PCI_CONFIG_EP (1 << 24) /* parity error */
+#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
+#define PCI_CONFIG_BM (1 << 22) /* bad master error */
+#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
+#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
+#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
+#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
+#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
+#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
+#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
+#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
+#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
+#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
+#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
+#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
+#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
+#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
+#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
+#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
+#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
+#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
+#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
+#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
+#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
+#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
+#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
+#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
+#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
+#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
+#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
+#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
+#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
+#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
+#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
+#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
+#define PCI_ID_VID(x) ((x) & 0xffff)
+#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
+#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
+#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
+#define PCI_CLASSREV_REV(x) ((x) & 0xff)
+#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
+#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
+#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
+#define PCI_PARAM_CLS(x) ((x) & 0xff)
+#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
+#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
+
#endif
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 4df8799..bb82cbd 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -18,14 +18,13 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
ops-bcm63xx.o
+obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
#
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
-obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
-obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
deleted file mode 100644
index e2ddfc4..0000000
--- a/arch/mips/pci/fixup-au1000.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Board specific PCI fixups.
- *
- * Copyright 2001-2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/pci.h>
-#include <linux/init.h>
-
-extern char irq_tab_alchemy[][5];
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- return irq_tab_alchemy[slot][pin];
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
deleted file mode 100644
index 9a57c5a..0000000
--- a/arch/mips/pci/ops-au1000.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Alchemy/AMD Au1xx0 PCI support.
- *
- * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * Support for all devices (greater than 16) added by David Gathright.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/vmalloc.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(KERN_DEBUG x)
-#else
-#define DBG(x...)
-#endif
-
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-int (*board_pci_idsel)(unsigned int devsel, int assert);
-
-void mod_wired_entry(int entry, unsigned long entrylo0,
- unsigned long entrylo1, unsigned long entryhi,
- unsigned long pagemask)
-{
- unsigned long old_pagemask;
- unsigned long old_ctx;
-
- /* Save old context and create impossible VPN2 value */
- old_ctx = read_c0_entryhi() & 0xff;
- old_pagemask = read_c0_pagemask();
- write_c0_index(entry);
- write_c0_pagemask(pagemask);
- write_c0_entryhi(entryhi);
- write_c0_entrylo0(entrylo0);
- write_c0_entrylo1(entrylo1);
- tlb_write_indexed();
- write_c0_entryhi(old_ctx);
- write_c0_pagemask(old_pagemask);
-}
-
-static struct vm_struct *pci_cfg_vm;
-static int pci_cfg_wired_entry;
-static unsigned long last_entryLo0, last_entryLo1;
-
-/*
- * We can't ioremap the entire pci config space because it's too large.
- * Nor can we call ioremap dynamically because some device drivers use
- * the PCI config routines from within interrupt handlers and that
- * becomes a problem in get_vm_area(). We use one wired TLB to handle
- * all config accesses for all busses.
- */
-void __init au1x_pci_cfg_init(void)
-{
- /* Reserve a wired entry for PCI config accesses */
- pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
- if (!pci_cfg_vm)
- panic(KERN_ERR "PCI unable to get vm area\n");
- pci_cfg_wired_entry = read_c0_wired();
- add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
- last_entryLo0 = last_entryLo1 = 0xffffffff;
-}
-
-static int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int dev_fn, unsigned char where, u32 *data)
-{
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
- unsigned int device = PCI_SLOT(dev_fn);
- unsigned int function = PCI_FUNC(dev_fn);
- unsigned long offset, status;
- unsigned long cfg_base;
- unsigned long flags;
- int error = PCIBIOS_SUCCESSFUL;
- unsigned long entryLo0, entryLo1;
-
- if (device > 19) {
- *data = 0xffffffff;
- return -1;
- }
-
- local_irq_save(flags);
- au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
- Au1500_PCI_STATCMD);
- au_sync_udelay(1);
-
- /*
- * Allow board vendors to implement their own off-chip IDSEL.
- * If it doesn't succeed, may as well bail out at this point.
- */
- if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {
- *data = 0xffffffff;
- local_irq_restore(flags);
- return -1;
- }
-
- /* Setup the config window */
- if (bus->number == 0)
- cfg_base = (1 << device) << 11;
- else
- cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
-
- /* Setup the lower bits of the 36-bit address */
- offset = (function << 8) | (where & ~0x3);
- /* Pick up any address that falls below the page mask */
- offset |= cfg_base & ~PAGE_MASK;
-
- /* Page boundary */
- cfg_base = cfg_base & PAGE_MASK;
-
- /*
- * To improve performance, if the current device is the same as
- * the last device accessed, we don't touch the TLB.
- */
- entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
- entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
- if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
- mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
- (unsigned long)pci_cfg_vm->addr, PM_4K);
- last_entryLo0 = entryLo0;
- last_entryLo1 = entryLo1;
- }
-
- if (access_type == PCI_ACCESS_WRITE)
- au_writel(*data, (int)(pci_cfg_vm->addr + offset));
- else
- *data = au_readl((int)(pci_cfg_vm->addr + offset));
-
- au_sync_udelay(2);
-
- DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",
- access_type, bus->number, device, where, *data, offset);
-
- /* Check master abort */
- status = au_readl(Au1500_PCI_STATCMD);
-
- if (status & (1 << 29)) {
- *data = 0xffffffff;
- error = -1;
- DBG("Au1x Master Abort\n");
- } else if ((status >> 28) & 0xf) {
- DBG("PCI ERR detected: device %u, status %lx\n",
- device, (status >> 28) & 0xf);
-
- /* Clear errors */
- au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
-
- *data = 0xffffffff;
- error = -1;
- }
-
- /* Take away the IDSEL. */
- if (board_pci_idsel)
- (void)board_pci_idsel(device, 0);
-
- local_irq_restore(flags);
- return error;
-#endif
-}
-
-static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
- int where, u8 *val)
-{
- u32 data;
- int ret;
-
- ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
- if (where & 1)
- data >>= 8;
- if (where & 2)
- data >>= 16;
- *val = data & 0xff;
- return ret;
-}
-
-static int read_config_word(struct pci_bus *bus, unsigned int devfn,
- int where, u16 *val)
-{
- u32 data;
- int ret;
-
- ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
- if (where & 2)
- data >>= 16;
- *val = data & 0xffff;
- return ret;
-}
-
-static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, u32 *val)
-{
- int ret;
-
- ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
- return ret;
-}
-
-static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
- int where, u8 val)
-{
- u32 data = 0;
-
- if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return -1;
-
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
-
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int write_config_word(struct pci_bus *bus, unsigned int devfn,
- int where, u16 val)
-{
- u32 data = 0;
-
- if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return -1;
-
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
-
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, u32 val)
-{
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int config_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- switch (size) {
- case 1: {
- u8 _val;
- int rc = read_config_byte(bus, devfn, where, &_val);
-
- *val = _val;
- return rc;
- }
- case 2: {
- u16 _val;
- int rc = read_config_word(bus, devfn, where, &_val);
-
- *val = _val;
- return rc;
- }
- default:
- return read_config_dword(bus, devfn, where, val);
- }
-}
-
-static int config_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- switch (size) {
- case 1:
- return write_config_byte(bus, devfn, where, (u8) val);
- case 2:
- return write_config_word(bus, devfn, where, (u16) val);
- default:
- return write_config_dword(bus, devfn, where, val);
- }
-}
-
-struct pci_ops au1x_pci_ops = {
- config_read,
- config_write
-};
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
new file mode 100644
index 0000000..4ee5710
--- /dev/null
+++ b/arch/mips/pci/pci-alchemy.c
@@ -0,0 +1,516 @@
+/*
+ * Alchemy PCI host mode support.
+ *
+ * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * Support for all devices (greater than 16) added by David Gathright.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+#ifdef CONFIG_DEBUG_PCI
+#define DBG(x...) printk(KERN_DEBUG x)
+#else
+#define DBG(x...) do {} while (0)
+#endif
+
+#define PCI_ACCESS_READ 0
+#define PCI_ACCESS_WRITE 1
+
+struct alchemy_pci_context {
+ struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
+ void __iomem *regs; /* ctrl base */
+ /* tools for wired entry for config space access */
+ unsigned long last_elo0;
+ unsigned long last_elo1;
+ int wired_entry;
+ struct vm_struct *pci_cfg_vm;
+
+ unsigned long pm[12];
+
+ int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
+ int (*board_pci_idsel)(unsigned int devsel, int assert);
+};
+
+/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
+ * in arch/mips/alchemy/common/setup.c
+ */
+static struct resource alchemy_pci_def_memres = {
+ .start = ALCHEMY_PCI_MEMWIN_START,
+ .end = ALCHEMY_PCI_MEMWIN_END,
+ .name = "PCI memory space",
+ .flags = IORESOURCE_MEM
+};
+
+static struct resource alchemy_pci_def_iores = {
+ .start = ALCHEMY_PCI_IOWIN_START,
+ .end = ALCHEMY_PCI_IOWIN_END,
+ .name = "PCI IO space",
+ .flags = IORESOURCE_IO
+};
+
+static void mod_wired_entry(int entry, unsigned long entrylo0,
+ unsigned long entrylo1, unsigned long entryhi,
+ unsigned long pagemask)
+{
+ unsigned long old_pagemask;
+ unsigned long old_ctx;
+
+ /* Save old context and create impossible VPN2 value */
+ old_ctx = read_c0_entryhi() & 0xff;
+ old_pagemask = read_c0_pagemask();
+ write_c0_index(entry);
+ write_c0_pagemask(pagemask);
+ write_c0_entryhi(entryhi);
+ write_c0_entrylo0(entrylo0);
+ write_c0_entrylo1(entrylo1);
+ tlb_write_indexed();
+ write_c0_entryhi(old_ctx);
+ write_c0_pagemask(old_pagemask);
+}
+
+static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
+{
+ ctx->wired_entry = read_c0_wired();
+ add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
+ ctx->last_elo0 = ctx->last_elo1 = ~0;
+}
+
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+ unsigned int dev_fn, unsigned char where, u32 *data)
+{
+ struct alchemy_pci_context *ctx = bus->sysdata;
+ unsigned int device = PCI_SLOT(dev_fn);
+ unsigned int function = PCI_FUNC(dev_fn);
+ unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
+ int error = PCIBIOS_SUCCESSFUL;
+
+ if (device > 19) {
+ *data = 0xffffffff;
+ return -1;
+ }
+
+ /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
+ * on resume, clearing our wired entry. Unfortunately the ->resume()
+ * callback is called way way way too late (and ->suspend() too early)
+ * to have them destroy and recreate it. Instead just test if c0_wired
+ * is now lower than the index we retrieved before suspending and then
+ * recreate the entry if necessary. Of course this is totally bonkers
+ * and breaks as soon as someone else adds another wired entry somewhere
+ * else. Anyone have any ideas how to handle this better?
+ */
+ if (unlikely(read_c0_wired() < ctx->wired_entry))
+ alchemy_pci_wired_entry(ctx);
+
+ local_irq_save(flags);
+ r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
+ r |= PCI_STATCMD_STATUS(0x2000);
+ __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
+ wmb();
+
+ /* Allow board vendors to implement their own off-chip IDSEL.
+ * If it doesn't succeed, may as well bail out at this point.
+ */
+ if (ctx->board_pci_idsel(device, 1) == 0) {
+ *data = 0xffffffff;
+ local_irq_restore(flags);
+ return -1;
+ }
+
+ /* Setup the config window */
+ if (bus->number == 0)
+ cfg_base = (1 << device) << 11;
+ else
+ cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
+
+ /* Setup the lower bits of the 36-bit address */
+ offset = (function << 8) | (where & ~0x3);
+ /* Pick up any address that falls below the page mask */
+ offset |= cfg_base & ~PAGE_MASK;
+
+ /* Page boundary */
+ cfg_base = cfg_base & PAGE_MASK;
+
+ /* To improve performance, if the current device is the same as
+ * the last device accessed, we don't touch the TLB.
+ */
+ entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
+ entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
+ if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
+ mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
+ (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
+ ctx->last_elo0 = entryLo0;
+ ctx->last_elo1 = entryLo1;
+ }
+
+ if (access_type == PCI_ACCESS_WRITE)
+ __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
+ else
+ *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
+ wmb();
+
+ DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
+ access_type, bus->number, device, where, *data, offset);
+
+ /* check for errors, master abort */
+ status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
+ if (status & (1 << 29)) {
+ *data = 0xffffffff;
+ error = -1;
+ DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
+ access_type, bus->number, device);
+ } else if ((status >> 28) & 0xf) {
+ DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
+ device, (status >> 28) & 0xf);
+
+ /* clear errors */
+ __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
+
+ *data = 0xffffffff;
+ error = -1;
+ }
+
+ /* Take away the IDSEL. */
+ (void)ctx->board_pci_idsel(device, 0);
+
+ local_irq_restore(flags);
+ return error;
+}
+
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u8 *val)
+{
+ u32 data;
+ int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+
+ if (where & 1)
+ data >>= 8;
+ if (where & 2)
+ data >>= 16;
+ *val = data & 0xff;
+ return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u16 *val)
+{
+ u32 data;
+ int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+
+ if (where & 2)
+ data >>= 16;
+ *val = data & 0xffff;
+ return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *val)
+{
+ return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+}
+
+static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u8 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u16 val)
+{
+ u32 data = 0;
+
+ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+ return -1;
+
+ data = (data & ~(0xffff << ((where & 3) << 3))) |
+ (val << ((where & 3) << 3));
+
+ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+ return -1;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 val)
+{
+ return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
+}
+
+static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ switch (size) {
+ case 1: {
+ u8 _val;
+ int rc = read_config_byte(bus, devfn, where, &_val);
+
+ *val = _val;
+ return rc;
+ }
+ case 2: {
+ u16 _val;
+ int rc = read_config_word(bus, devfn, where, &_val);
+
+ *val = _val;
+ return rc;
+ }
+ default:
+ return read_config_dword(bus, devfn, where, val);
+ }
+}
+
+static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ switch (size) {
+ case 1:
+ return write_config_byte(bus, devfn, where, (u8) val);
+ case 2:
+ return write_config_word(bus, devfn, where, (u16) val);
+ default:
+ return write_config_dword(bus, devfn, where, val);
+ }
+}
+
+static struct pci_ops alchemy_pci_ops = {
+ .read = alchemy_pci_read,
+ .write = alchemy_pci_write,
+};
+
+static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
+{
+ return 1; /* success */
+}
+
+static int __devinit alchemy_pci_probe(struct platform_device *pdev)
+{
+ struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
+ struct alchemy_pci_context *ctx;
+ void __iomem *virt_io;
+ unsigned long val;
+ struct resource *r;
+ int ret;
+
+ /* need at least PCI IRQ mapping table */
+ if (!pd) {
+ dev_err(&pdev->dev, "need platform data for PCI setup\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx) {
+ dev_err(&pdev->dev, "no memory for pcictl context\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!r) {
+ dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
+ ret = -ENODEV;
+ goto out1;
+ }
+
+ if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
+ dev_err(&pdev->dev, "cannot claim pci regs\n");
+ ret = -ENODEV;
+ goto out1;
+ }
+
+ ctx->regs = ioremap_nocache(r->start, resource_size(r));
+ if (!ctx->regs) {
+ dev_err(&pdev->dev, "cannot map pci regs\n");
+ ret = -ENODEV;
+ goto out2;
+ }
+
+ /* map parts of the PCI IO area */
+ /* REVISIT: if this changes with a newer variant (doubt it) make this
+ * a platform resource.
+ */
+ virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
+ if (!virt_io) {
+ dev_err(&pdev->dev, "cannot remap pci io space\n");
+ ret = -ENODEV;
+ goto out3;
+ }
+ ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
+
+#ifdef CONFIG_DMA_NONCOHERENT
+ /* Au1500 revisions older than AD have borked coherent PCI */
+ if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
+ (read_c0_prid() < 0x01030202)) {
+ val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
+ val |= PCI_CONFIG_NC;
+ __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
+ wmb();
+ dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
+ }
+#endif
+
+ if (pd->board_map_irq)
+ ctx->board_map_irq = pd->board_map_irq;
+
+ if (pd->board_pci_idsel)
+ ctx->board_pci_idsel = pd->board_pci_idsel;
+ else
+ ctx->board_pci_idsel = alchemy_pci_def_idsel;
+
+ /* fill in relevant pci_controller members */
+ ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
+ ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
+ ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
+
+ /* we can't ioremap the entire pci config space because it's too large,
+ * nor can we dynamically ioremap it because some drivers use the
+ * PCI config routines from within atomic contex and that becomes a
+ * problem in get_vm_area(). Instead we use one wired TLB entry to
+ * handle all config accesses for all busses.
+ */
+ ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
+ if (!ctx->pci_cfg_vm) {
+ dev_err(&pdev->dev, "unable to get vm area\n");
+ ret = -ENOMEM;
+ goto out4;
+ }
+ ctx->wired_entry = 8192; /* impossibly high value */
+
+ set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
+
+ /* board may want to modify bits in the config register, do it now */
+ val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
+ val &= ~pd->pci_cfg_clr;
+ val |= pd->pci_cfg_set;
+ val &= ~PCI_CONFIG_PD; /* clear disable bit */
+ __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
+ wmb();
+
+ platform_set_drvdata(pdev, ctx);
+ register_pci_controller(&ctx->alchemy_pci_ctrl);
+
+ return 0;
+
+out4:
+ iounmap(virt_io);
+out3:
+ iounmap(ctx->regs);
+out2:
+ release_mem_region(r->start, resource_size(r));
+out1:
+ kfree(ctx);
+out:
+ return ret;
+}
+
+
+#ifdef CONFIG_PM
+/* save PCI controller register contents. */
+static int alchemy_pci_suspend(struct device *dev)
+{
+ struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
+
+ ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM);
+ ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
+ ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
+ ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
+ ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
+ ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
+ ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
+ ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID);
+ ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
+ ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM);
+ ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
+ ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
+
+ return 0;
+}
+
+static int alchemy_pci_resume(struct device *dev)
+{
+ struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
+
+ __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM);
+ __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH);
+ __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID);
+ __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID);
+ __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV);
+ __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL);
+ __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID);
+ __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV);
+ __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM);
+ __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
+ __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
+ wmb();
+ __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG);
+ wmb();
+
+ return 0;
+}
+
+static const struct dev_pm_ops alchemy_pci_pmops = {
+ .suspend = alchemy_pci_suspend,
+ .resume = alchemy_pci_resume,
+};
+
+#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops)
+
+#else
+#define ALCHEMY_PCICTL_PM NULL
+#endif
+
+static struct platform_driver alchemy_pcictl_driver = {
+ .probe = alchemy_pci_probe,
+ .driver = {
+ .name = "alchemy-pci",
+ .owner = THIS_MODULE,
+ .pm = ALCHEMY_PCICTL_PM,
+ },
+};
+
+static int __init alchemy_pci_init(void)
+{
+ /* Au1500/Au1550 have PCI */
+ switch (alchemy_get_cputype()) {
+ case ALCHEMY_CPU_AU1500:
+ case ALCHEMY_CPU_AU1550:
+ return platform_driver_register(&alchemy_pcictl_driver);
+ }
+ return 0;
+}
+arch_initcall(alchemy_pci_init);
+
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ struct alchemy_pci_context *ctx = dev->sysdata;
+ if (ctx && ctx->board_map_irq)
+ return ctx->board_map_irq(dev, slot, pin);
+ return -1;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 8/8] MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
2011-08-12 9:39 [PATCH RESEND 0/8] MIPS: Alchemy updates Manuel Lauss
` (6 preceding siblings ...)
2011-08-12 9:39 ` [PATCH 7/8] MIPS: Alchemy: redo PCI as platform driver Manuel Lauss
@ 2011-08-12 9:39 ` Manuel Lauss
2011-08-18 19:13 ` Ralf Baechle
7 siblings, 1 reply; 21+ messages in thread
From: Manuel Lauss @ 2011-08-12 9:39 UTC (permalink / raw)
To: Linux-MIPS, Ralf Baechle; +Cc: Manuel Lauss
Now that no driver any longer depends on the CONFIG_SOC_AU1???
symbols, it's time to get rid of them:
Move some of the platform devices to the boards which can use them,
Rename a few (unused) constants in the header,
Replace them with MIPS_ALCHEMY in the various Kconfig files.
Finally delete them altogether from the Alchemy Kconfig file.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
---
This patch will throw merge conflicts with changes in the ASoC tree.
arch/mips/Kconfig | 2 +
arch/mips/alchemy/Kconfig | 50 ++----
arch/mips/alchemy/common/platform.c | 175 +------------------
arch/mips/alchemy/devboards/db1200/platform.c | 78 ++++++++-
arch/mips/alchemy/devboards/db1x00/board_setup.c | 4 +-
arch/mips/alchemy/devboards/db1x00/platform.c | 32 ++++
arch/mips/alchemy/devboards/pb1100/platform.c | 29 +++
arch/mips/alchemy/devboards/pb1200/platform.c | 137 ++++++++++++++-
arch/mips/alchemy/devboards/pb1500/platform.c | 1 +
arch/mips/alchemy/devboards/pb1550/platform.c | 33 ++++
arch/mips/include/asm/mach-au1x00/au1000.h | 203 ++++++++++------------
drivers/i2c/busses/Kconfig | 2 +-
drivers/ide/Kconfig | 6 +-
drivers/mmc/host/Kconfig | 2 +-
drivers/mtd/nand/Kconfig | 2 +-
drivers/net/irda/Kconfig | 2 +-
drivers/spi/Kconfig | 2 +-
drivers/usb/Kconfig | 1 -
drivers/usb/host/ehci-hcd.c | 2 +-
drivers/video/Kconfig | 4 +-
sound/mips/Kconfig | 2 +-
sound/soc/au1x/Kconfig | 2 +-
22 files changed, 423 insertions(+), 348 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 177cdaf..32e7e3c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -46,6 +46,8 @@ config MIPS_ALCHEMY
select GENERIC_GPIO
select ARCH_WANT_OPTIONAL_GPIOLIB
select SYS_SUPPORTS_ZBOOT
+ select USB_ARCH_HAS_OHCI
+ select USB_ARCH_HAS_EHCI
config AR7
bool "Texas Instruments AR7"
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2ccfd4a..2a68be6 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -18,20 +18,20 @@ config MIPS_MTX1
bool "4G Systems MTX-1 board"
select DMA_NONCOHERENT
select HW_HAS_PCI
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_BOSPORUS
bool "Alchemy Bosporus board"
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_DB1000
bool "Alchemy DB1000 board"
- select SOC_AU1000
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -39,14 +39,14 @@ config MIPS_DB1000
config MIPS_DB1100
bool "Alchemy DB1100 board"
- select SOC_AU1100
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_DB1200
bool "Alchemy DB1200 board"
- select SOC_AU1200
+ select ALCHEMY_GPIOINT_AU1000
select DMA_COHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -54,7 +54,7 @@ config MIPS_DB1200
config MIPS_DB1500
bool "Alchemy DB1500 board"
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
@@ -64,7 +64,7 @@ config MIPS_DB1500
config MIPS_DB1550
bool "Alchemy DB1550 board"
- select SOC_AU1550
+ select ALCHEMY_GPIOINT_AU1000
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
@@ -74,13 +74,13 @@ config MIPS_DB1550
config MIPS_MIRAGE
bool "Alchemy Mirage board"
select DMA_NONCOHERENT
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_PB1000
bool "Alchemy PB1000 board"
- select SOC_AU1000
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
@@ -89,7 +89,7 @@ config MIPS_PB1000
config MIPS_PB1100
bool "Alchemy PB1100 board"
- select SOC_AU1100
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
@@ -98,7 +98,7 @@ config MIPS_PB1100
config MIPS_PB1200
bool "Alchemy PB1200 board"
- select SOC_AU1200
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -106,7 +106,7 @@ config MIPS_PB1200
config MIPS_PB1500
bool "Alchemy PB1500 board"
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -114,7 +114,7 @@ config MIPS_PB1500
config MIPS_PB1550
bool "Alchemy PB1550 board"
- select SOC_AU1550
+ select ALCHEMY_GPIOINT_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
@@ -124,13 +124,13 @@ config MIPS_PB1550
config MIPS_XXS1500
bool "MyCable XXS1500 board"
select DMA_NONCOHERENT
- select SOC_AU1500
+ select ALCHEMY_GPIOINT_AU1000
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
config MIPS_GPR
bool "Trapeze ITS GPR board"
- select SOC_AU1550
+ select ALCHEMY_GPIOINT_AU1000
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
@@ -138,23 +138,3 @@ config MIPS_GPR
select SYS_HAS_EARLY_PRINTK
endchoice
-
-config SOC_AU1000
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1100
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1500
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1550
- bool
- select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1200
- bool
- select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 657ae27..c8e5d72 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -189,159 +189,6 @@ static void __init alchemy_setup_usb(int ctype)
}
}
-/*** AU1100 LCD controller ***/
-
-#ifdef CONFIG_FB_AU1100
-static struct resource au1100_lcd_resources[] = {
- [0] = {
- .start = AU1100_LCD_PHYS_ADDR,
- .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1100_LCD_INT,
- .end = AU1100_LCD_INT,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1100_lcd_device = {
- .name = "au1100-lcd",
- .id = 0,
- .dev = {
- .dma_mask = &au1100_lcd_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1100_lcd_resources),
- .resource = au1100_lcd_resources,
-};
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-
-static struct resource au1200_lcd_resources[] = {
- [0] = {
- .start = AU1200_LCD_PHYS_ADDR,
- .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_LCD_INT,
- .end = AU1200_LCD_INT,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1200_lcd_device = {
- .name = "au1200-lcd",
- .id = 0,
- .dev = {
- .dma_mask = &au1200_lcd_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(au1200_lcd_resources),
- .resource = au1200_lcd_resources,
-};
-
-static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
-
-extern struct au1xmmc_platform_data au1xmmc_platdata[2];
-
-static struct resource au1200_mmc0_resources[] = {
- [0] = {
- .start = AU1100_SD0_PHYS_ADDR,
- .end = AU1100_SD0_PHYS_ADDR + 0xfff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_SD_INT,
- .end = AU1200_SD_INT,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = AU1200_DSCR_CMD0_SDMS_TX0,
- .end = AU1200_DSCR_CMD0_SDMS_TX0,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = AU1200_DSCR_CMD0_SDMS_RX0,
- .end = AU1200_DSCR_CMD0_SDMS_RX0,
- .flags = IORESOURCE_DMA,
- }
-};
-
-static struct platform_device au1200_mmc0_device = {
- .name = "au1xxx-mmc",
- .id = 0,
- .dev = {
- .dma_mask = &au1xxx_mmc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &au1xmmc_platdata[0],
- },
- .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
- .resource = au1200_mmc0_resources,
-};
-
-#ifndef CONFIG_MIPS_DB1200
-static struct resource au1200_mmc1_resources[] = {
- [0] = {
- .start = AU1100_SD1_PHYS_ADDR,
- .end = AU1100_SD1_PHYS_ADDR + 0xfff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = AU1200_SD_INT,
- .end = AU1200_SD_INT,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = AU1200_DSCR_CMD0_SDMS_TX1,
- .end = AU1200_DSCR_CMD0_SDMS_TX1,
- .flags = IORESOURCE_DMA,
- },
- [3] = {
- .start = AU1200_DSCR_CMD0_SDMS_RX1,
- .end = AU1200_DSCR_CMD0_SDMS_RX1,
- .flags = IORESOURCE_DMA,
- }
-};
-
-static struct platform_device au1200_mmc1_device = {
- .name = "au1xxx-mmc",
- .id = 1,
- .dev = {
- .dma_mask = &au1xxx_mmc_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &au1xmmc_platdata[1],
- },
- .num_resources = ARRAY_SIZE(au1200_mmc1_resources),
- .resource = au1200_mmc1_resources,
-};
-#endif /* #ifndef CONFIG_MIPS_DB1200 */
-#endif /* #ifdef CONFIG_SOC_AU1200 */
-
-/* All Alchemy demoboards with I2C have this #define in their headers */
-#ifdef SMBUS_PSC_BASE
-static struct resource pbdb_smbus_resources[] = {
- {
- .start = SMBUS_PSC_BASE,
- .end = SMBUS_PSC_BASE + 0xfff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device pbdb_smbus_device = {
- .name = "au1xpsc_smbus",
- .id = 0, /* bus number */
- .num_resources = ARRAY_SIZE(pbdb_smbus_resources),
- .resource = pbdb_smbus_resources,
-};
-#endif
-
/* Macro to help defining the Ethernet MAC resources */
#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
#define MAC_RES(_base, _enable, _irq, _macdma) \
@@ -503,33 +350,15 @@ static void __init alchemy_setup_macs(int ctype)
}
}
-static struct platform_device *au1xxx_platform_devices[] __initdata = {
-#ifdef CONFIG_FB_AU1100
- &au1100_lcd_device,
-#endif
-#ifdef CONFIG_SOC_AU1200
- &au1200_lcd_device,
- &au1200_mmc0_device,
-#ifndef CONFIG_MIPS_DB1200
- &au1200_mmc1_device,
-#endif
-#endif
-#ifdef SMBUS_PSC_BASE
- &pbdb_smbus_device,
-#endif
-};
-
static int __init au1xxx_platform_init(void)
{
- int err, ctype = alchemy_get_cputype();
+ int ctype = alchemy_get_cputype();
alchemy_setup_uarts(ctype);
alchemy_setup_macs(ctype);
alchemy_setup_usb(ctype);
- err = platform_add_devices(au1xxx_platform_devices,
- ARRAY_SIZE(au1xxx_platform_devices));
- return err;
+ return 0;
}
arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 1bc16f0..aae08c1 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -333,15 +333,77 @@ static struct led_classdev db1200_mmc_led = {
.brightness_set = db1200_mmcled_set,
};
-/* needed by arch/mips/alchemy/common/platform.c */
-struct au1xmmc_platform_data au1xmmc_platdata[] = {
+static struct au1xmmc_platform_data db1200mmc_platdata = {
+ .cd_setup = db1200_mmc_cd_setup,
+ .set_power = db1200_mmc_set_power,
+ .card_inserted = db1200_mmc_card_inserted,
+ .card_readonly = db1200_mmc_card_readonly,
+ .led = &db1200_mmc_led,
+};
+
+static struct resource au1200_mmc0_resources[] = {
+ [0] = {
+ .start = AU1100_SD0_PHYS_ADDR,
+ .end = AU1100_SD0_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_SD_INT,
+ .end = AU1200_SD_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_SDMS_TX0,
+ .end = AU1200_DSCR_CMD0_SDMS_TX0,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_SDMS_RX0,
+ .end = AU1200_DSCR_CMD0_SDMS_RX0,
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device db1200_mmc0_dev = {
+ .name = "au1xxx-mmc",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1xxx_mmc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &db1200mmc_platdata,
+ },
+ .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
+ .resource = au1200_mmc0_resources,
+};
+
+/**********************************************************************/
+
+static struct resource au1200_lcd_res[] = {
[0] = {
- .cd_setup = db1200_mmc_cd_setup,
- .set_power = db1200_mmc_set_power,
- .card_inserted = db1200_mmc_card_inserted,
- .card_readonly = db1200_mmc_card_readonly,
- .led = &db1200_mmc_led,
+ .start = AU1200_LCD_PHYS_ADDR,
+ .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_LCD_INT,
+ .end = AU1200_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1200_lcd_dev = {
+ .name = "au1200-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1200_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
+ .num_resources = ARRAY_SIZE(au1200_lcd_res),
+ .resource = au1200_lcd_res,
};
/**********************************************************************/
@@ -442,6 +504,8 @@ static struct platform_device db1200_stac_dev = {
static struct platform_device *db1200_devs[] __initdata = {
NULL, /* PSC0, selected by S6.8 */
&db1200_ide_dev,
+ &db1200_mmc0_dev,
+ &au1200_lcd_dev,
&db1200_eth_dev,
&db1200_rtc_dev,
&db1200_nand_dev,
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 2b2178f..7cd36e6 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -134,9 +134,7 @@ void __init board_setup(void)
/* initialize board register space */
bcsr_init(bcsr1, bcsr2);
- /* Not valid for Au1550 */
-#if defined(CONFIG_IRDA) && \
- (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
+#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
{
u32 pin_func;
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 990367f..8704865 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -19,6 +19,7 @@
*/
#include <linux/init.h>
+#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
@@ -208,6 +209,34 @@ static int __init db15x0_pci_init(void)
arch_initcall(db15x0_pci_init);
#endif
+#ifdef CONFIG_MIPS_DB1100
+static struct resource au1100_lcd_resources[] = {
+ [0] = {
+ .start = AU1100_LCD_PHYS_ADDR,
+ .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1100_LCD_INT,
+ .end = AU1100_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1100_lcd_device = {
+ .name = "au1100-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1100_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(au1100_lcd_resources),
+ .resource = au1100_lcd_resources,
+};
+#endif
+
static int __init db1xxx_dev_init(void)
{
#ifdef DB1XXX_HAS_PCMCIA
@@ -231,6 +260,9 @@ static int __init db1xxx_dev_init(void)
DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
/*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
#endif
+#ifdef CONFIG_MIPS_DB1100
+ platform_device_register(&au1100_lcd_device);
+#endif
db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
return 0;
}
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
index 8a4e733..9c57c01 100644
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -19,12 +19,40 @@
*/
#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../platform.h"
+static struct resource au1100_lcd_resources[] = {
+ [0] = {
+ .start = AU1100_LCD_PHYS_ADDR,
+ .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1100_LCD_INT,
+ .end = AU1100_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1100_lcd_device = {
+ .name = "au1100-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1100_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(au1100_lcd_resources),
+ .resource = au1100_lcd_resources,
+};
+
static int __init pb1100_dev_init(void)
{
int swapped;
@@ -42,6 +70,7 @@ static int __init pb1100_dev_init(void)
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+ platform_device_register(&au1100_lcd_device);
return 0;
}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index d7915b0..54f7f7b 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -90,7 +90,7 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
}
-const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
+static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
[0] = {
.set_power = pb1200mmc0_set_power,
.card_inserted = pb1200mmc0_card_inserted,
@@ -107,6 +107,79 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
},
};
+static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
+
+static struct resource au1200_mmc0_res[] = {
+ [0] = {
+ .start = AU1100_SD0_PHYS_ADDR,
+ .end = AU1100_SD0_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_SD_INT,
+ .end = AU1200_SD_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_SDMS_TX0,
+ .end = AU1200_DSCR_CMD0_SDMS_TX0,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_SDMS_RX0,
+ .end = AU1200_DSCR_CMD0_SDMS_RX0,
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static struct platform_device pb1200_mmc0_dev = {
+ .name = "au1xxx-mmc",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1xxx_mmc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &pb1200mmc_platdata[0],
+ },
+ .num_resources = ARRAY_SIZE(au1200_mmc0_res),
+ .resource = au1200_mmc0_res,
+};
+
+static struct resource au1200_mmc1_res[] = {
+ [0] = {
+ .start = AU1100_SD1_PHYS_ADDR,
+ .end = AU1100_SD1_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_SD_INT,
+ .end = AU1200_SD_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_SDMS_TX1,
+ .end = AU1200_DSCR_CMD0_SDMS_TX1,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_SDMS_RX1,
+ .end = AU1200_DSCR_CMD0_SDMS_RX1,
+ .flags = IORESOURCE_DMA,
+ }
+};
+
+static struct platform_device pb1200_mmc1_dev = {
+ .name = "au1xxx-mmc",
+ .id = 1,
+ .dev = {
+ .dma_mask = &au1xxx_mmc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &pb1200mmc_platdata[1],
+ },
+ .num_resources = ARRAY_SIZE(au1200_mmc1_res),
+ .resource = au1200_mmc1_res,
+};
+
+
static struct resource ide_resources[] = {
[0] = {
.start = IDE_PHYS_ADDR,
@@ -168,9 +241,69 @@ static struct platform_device smc91c111_device = {
.resource = smc91c111_resources
};
+static struct resource au1200_psc0_res[] = {
+ [0] = {
+ .start = AU1550_PSC0_PHYS_ADDR,
+ .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_PSC0_INT,
+ .end = AU1200_PSC0_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1200_DSCR_CMD0_PSC0_TX,
+ .end = AU1200_DSCR_CMD0_PSC0_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1200_DSCR_CMD0_PSC0_RX,
+ .end = AU1200_DSCR_CMD0_PSC0_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct platform_device pb1200_i2c_dev = {
+ .name = "au1xpsc_smbus",
+ .id = 0, /* bus number */
+ .num_resources = ARRAY_SIZE(au1200_psc0_res),
+ .resource = au1200_psc0_res,
+};
+
+static struct resource au1200_lcd_res[] = {
+ [0] = {
+ .start = AU1200_LCD_PHYS_ADDR,
+ .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1200_LCD_INT,
+ .end = AU1200_LCD_INT,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1200_lcd_dev = {
+ .name = "au1200-lcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &au1200_lcd_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(au1200_lcd_res),
+ .resource = au1200_lcd_res,
+};
+
static struct platform_device *board_platform_devices[] __initdata = {
&ide_device,
- &smc91c111_device
+ &smc91c111_device,
+ &pb1200_i2c_dev,
+ &pb1200_mmc0_dev,
+ &pb1200_mmc1_dev,
+ &au1200_lcd_dev,
};
static int __init board_register_devices(void)
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index 9f0b5a0..1e52a01 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index 0c5711f..a4604b8 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -18,9 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-pb1x00/pb1550.h>
#include <asm/mach-db1x00/bcsr.h>
@@ -69,6 +71,36 @@ static struct platform_device pb1550_pci_host = {
.resource = alchemy_pci_host_res,
};
+static struct resource au1550_psc2_res[] = {
+ [0] = {
+ .start = AU1550_PSC2_PHYS_ADDR,
+ .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1550_PSC2_INT,
+ .end = AU1550_PSC2_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = AU1550_DSCR_CMD0_PSC2_TX,
+ .end = AU1550_DSCR_CMD0_PSC2_TX,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = AU1550_DSCR_CMD0_PSC2_RX,
+ .end = AU1550_DSCR_CMD0_PSC2_RX,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct platform_device pb1550_i2c_dev = {
+ .name = "au1xpsc_smbus",
+ .id = 0, /* bus number */
+ .num_resources = ARRAY_SIZE(au1550_psc2_res),
+ .resource = au1550_psc2_res,
+};
+
static int __init pb1550_dev_init(void)
{
int swapped;
@@ -101,6 +133,7 @@ static int __init pb1550_dev_init(void)
swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
platform_device_register(&pb1550_pci_host);
+ platform_device_register(&pb1550_i2c_dev);
return 0;
}
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 5da2fd7..4afc3a9 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -592,113 +592,6 @@ enum soc_au1200_ints {
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
/*
- * SDRAM register offsets
- */
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
- defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0 0x0000
-#define MEM_SDMODE1 0x0004
-#define MEM_SDMODE2 0x0008
-#define MEM_SDADDR0 0x000C
-#define MEM_SDADDR1 0x0010
-#define MEM_SDADDR2 0x0014
-#define MEM_SDREFCFG 0x0018
-#define MEM_SDPRECMD 0x001C
-#define MEM_SDAUTOREF 0x0020
-#define MEM_SDWRMD0 0x0024
-#define MEM_SDWRMD1 0x0028
-#define MEM_SDWRMD2 0x002C
-#define MEM_SDSLEEP 0x0030
-#define MEM_SDSMCKE 0x0034
-
-/*
- * MEM_SDMODE register content definitions
- */
-#define MEM_SDMODE_F (1 << 22)
-#define MEM_SDMODE_SR (1 << 21)
-#define MEM_SDMODE_BS (1 << 20)
-#define MEM_SDMODE_RS (3 << 18)
-#define MEM_SDMODE_CS (7 << 15)
-#define MEM_SDMODE_TRAS (15 << 11)
-#define MEM_SDMODE_TMRD (3 << 9)
-#define MEM_SDMODE_TWR (3 << 7)
-#define MEM_SDMODE_TRP (3 << 5)
-#define MEM_SDMODE_TRCD (3 << 3)
-#define MEM_SDMODE_TCL (7 << 0)
-
-#define MEM_SDMODE_BS_2Bank (0 << 20)
-#define MEM_SDMODE_BS_4Bank (1 << 20)
-#define MEM_SDMODE_RS_11Row (0 << 18)
-#define MEM_SDMODE_RS_12Row (1 << 18)
-#define MEM_SDMODE_RS_13Row (2 << 18)
-#define MEM_SDMODE_RS_N(N) ((N) << 18)
-#define MEM_SDMODE_CS_7Col (0 << 15)
-#define MEM_SDMODE_CS_8Col (1 << 15)
-#define MEM_SDMODE_CS_9Col (2 << 15)
-#define MEM_SDMODE_CS_10Col (3 << 15)
-#define MEM_SDMODE_CS_11Col (4 << 15)
-#define MEM_SDMODE_CS_N(N) ((N) << 15)
-#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
-#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
-#define MEM_SDMODE_TWR_N(N) ((N) << 7)
-#define MEM_SDMODE_TRP_N(N) ((N) << 5)
-#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
-#define MEM_SDMODE_TCL_N(N) ((N) << 0)
-
-/*
- * MEM_SDADDR register contents definitions
- */
-#define MEM_SDADDR_E (1 << 20)
-#define MEM_SDADDR_CSBA (0x03FF << 10)
-#define MEM_SDADDR_CSMASK (0x03FF << 0)
-#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
-#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
-
-/*
- * MEM_SDREFCFG register content definitions
- */
-#define MEM_SDREFCFG_TRC (15 << 28)
-#define MEM_SDREFCFG_TRPM (3 << 26)
-#define MEM_SDREFCFG_E (1 << 25)
-#define MEM_SDREFCFG_RE (0x1ffffff << 0)
-#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
-#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
-#define MEM_SDREFCFG_REF_N(N) (N)
-#endif
-
-/***********************************************************************/
-
-/*
- * Au1550 SDRAM Register Offsets
- */
-
-/***********************************************************************/
-
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_SDMODE0 0x0800
-#define MEM_SDMODE1 0x0808
-#define MEM_SDMODE2 0x0810
-#define MEM_SDADDR0 0x0820
-#define MEM_SDADDR1 0x0828
-#define MEM_SDADDR2 0x0830
-#define MEM_SDCONFIGA 0x0840
-#define MEM_SDCONFIGB 0x0848
-#define MEM_SDSTAT 0x0850
-#define MEM_SDERRADDR 0x0858
-#define MEM_SDSTRIDE0 0x0860
-#define MEM_SDSTRIDE1 0x0868
-#define MEM_SDSTRIDE2 0x0870
-#define MEM_SDWRMD0 0x0880
-#define MEM_SDWRMD1 0x0888
-#define MEM_SDWRMD2 0x0890
-#define MEM_SDPRECMD 0x08C0
-#define MEM_SDAUTOREF 0x08C8
-#define MEM_SDSREF 0x08D0
-#define MEM_SDSLEEP MEM_SDSREF
-
-#endif
-
-/*
* Physical base addresses for integrated peripherals
* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
*/
@@ -761,6 +654,92 @@ enum soc_au1200_ints {
#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
+/* Au1000 SDRAM memory controller register offsets */
+#define AU1000_MEM_SDMODE0 0x0000
+#define AU1000_MEM_SDMODE1 0x0004
+#define AU1000_MEM_SDMODE2 0x0008
+#define AU1000_MEM_SDADDR0 0x000C
+#define AU1000_MEM_SDADDR1 0x0010
+#define AU1000_MEM_SDADDR2 0x0014
+#define AU1000_MEM_SDREFCFG 0x0018
+#define AU1000_MEM_SDPRECMD 0x001C
+#define AU1000_MEM_SDAUTOREF 0x0020
+#define AU1000_MEM_SDWRMD0 0x0024
+#define AU1000_MEM_SDWRMD1 0x0028
+#define AU1000_MEM_SDWRMD2 0x002C
+#define AU1000_MEM_SDSLEEP 0x0030
+#define AU1000_MEM_SDSMCKE 0x0034
+
+/* MEM_SDMODE register content definitions */
+#define MEM_SDMODE_F (1 << 22)
+#define MEM_SDMODE_SR (1 << 21)
+#define MEM_SDMODE_BS (1 << 20)
+#define MEM_SDMODE_RS (3 << 18)
+#define MEM_SDMODE_CS (7 << 15)
+#define MEM_SDMODE_TRAS (15 << 11)
+#define MEM_SDMODE_TMRD (3 << 9)
+#define MEM_SDMODE_TWR (3 << 7)
+#define MEM_SDMODE_TRP (3 << 5)
+#define MEM_SDMODE_TRCD (3 << 3)
+#define MEM_SDMODE_TCL (7 << 0)
+
+#define MEM_SDMODE_BS_2Bank (0 << 20)
+#define MEM_SDMODE_BS_4Bank (1 << 20)
+#define MEM_SDMODE_RS_11Row (0 << 18)
+#define MEM_SDMODE_RS_12Row (1 << 18)
+#define MEM_SDMODE_RS_13Row (2 << 18)
+#define MEM_SDMODE_RS_N(N) ((N) << 18)
+#define MEM_SDMODE_CS_7Col (0 << 15)
+#define MEM_SDMODE_CS_8Col (1 << 15)
+#define MEM_SDMODE_CS_9Col (2 << 15)
+#define MEM_SDMODE_CS_10Col (3 << 15)
+#define MEM_SDMODE_CS_11Col (4 << 15)
+#define MEM_SDMODE_CS_N(N) ((N) << 15)
+#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
+#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
+#define MEM_SDMODE_TWR_N(N) ((N) << 7)
+#define MEM_SDMODE_TRP_N(N) ((N) << 5)
+#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
+#define MEM_SDMODE_TCL_N(N) ((N) << 0)
+
+/* MEM_SDADDR register contents definitions */
+#define MEM_SDADDR_E (1 << 20)
+#define MEM_SDADDR_CSBA (0x03FF << 10)
+#define MEM_SDADDR_CSMASK (0x03FF << 0)
+#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
+#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
+
+/* MEM_SDREFCFG register content definitions */
+#define MEM_SDREFCFG_TRC (15 << 28)
+#define MEM_SDREFCFG_TRPM (3 << 26)
+#define MEM_SDREFCFG_E (1 << 25)
+#define MEM_SDREFCFG_RE (0x1ffffff << 0)
+#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N) (N)
+
+/* Au1550 SDRAM Register Offsets */
+#define AU1550_MEM_SDMODE0 0x0800
+#define AU1550_MEM_SDMODE1 0x0808
+#define AU1550_MEM_SDMODE2 0x0810
+#define AU1550_MEM_SDADDR0 0x0820
+#define AU1550_MEM_SDADDR1 0x0828
+#define AU1550_MEM_SDADDR2 0x0830
+#define AU1550_MEM_SDCONFIGA 0x0840
+#define AU1550_MEM_SDCONFIGB 0x0848
+#define AU1550_MEM_SDSTAT 0x0850
+#define AU1550_MEM_SDERRADDR 0x0858
+#define AU1550_MEM_SDSTRIDE0 0x0860
+#define AU1550_MEM_SDSTRIDE1 0x0868
+#define AU1550_MEM_SDSTRIDE2 0x0870
+#define AU1550_MEM_SDWRMD0 0x0880
+#define AU1550_MEM_SDWRMD1 0x0888
+#define AU1550_MEM_SDWRMD2 0x0890
+#define AU1550_MEM_SDPRECMD 0x08C0
+#define AU1550_MEM_SDAUTOREF 0x08C8
+#define AU1550_MEM_SDSREF 0x08D0
+#define AU1550_MEM_SDSLEEP MEM_SDSREF
+
/* Static Bus Controller */
#define MEM_STCFG0 0xB4001000
#define MEM_STTIME0 0xB4001004
@@ -778,14 +757,12 @@ enum soc_au1200_ints {
#define MEM_STTIME3 0xB4001034
#define MEM_STADDR3 0xB4001038
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
#define MEM_STNDCTL 0xB4001100
#define MEM_STSTAT 0xB4001104
#define MEM_STNAND_CMD 0x0
#define MEM_STNAND_ADDR 0x4
#define MEM_STNAND_DATA 0x20
-#endif
/* Programmable Counters 0 and 1 */
@@ -1172,7 +1149,6 @@ enum soc_au1200_ints {
# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
/* Au1200 only */
-#ifdef CONFIG_SOC_AU1200
#define SYS_PINFUNC_DMA (1 << 31)
#define SYS_PINFUNC_S0A (1 << 30)
#define SYS_PINFUNC_S1A (1 << 29)
@@ -1200,7 +1176,6 @@ enum soc_au1200_ints {
#define SYS_PINFUNC_P0B (1 << 4)
#define SYS_PINFUNC_U0T (1 << 3)
#define SYS_PINFUNC_S1B (1 << 2)
-#endif
/* Power Management */
#define SYS_SCRATCH0 0xB1900018
@@ -1256,12 +1231,12 @@ enum soc_au1200_ints {
# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
# define SYS_CS_DI2 (1 << 16)
# define SYS_CS_CI2 (1 << 15)
-#ifdef CONFIG_SOC_AU1100
+
# define SYS_CS_ML_BIT 7
# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
# define SYS_CS_DL (1 << 6)
# define SYS_CS_CL (1 << 5)
-#else
+
# define SYS_CS_MUH_BIT 12
# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
# define SYS_CS_DUH (1 << 11)
@@ -1270,7 +1245,7 @@ enum soc_au1200_ints {
# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
# define SYS_CS_DUD (1 << 6)
# define SYS_CS_CUD (1 << 5)
-#endif
+
# define SYS_CS_MIR_BIT 2
# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
# define SYS_CS_DIR (1 << 1)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 646068e..1908195 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -301,7 +301,7 @@ config I2C_AT91
config I2C_AU1550
tristate "Au1550/Au1200 SMBus interface"
- depends on SOC_AU1550 || SOC_AU1200
+ depends on MIPS_ALCHEMY
help
If you say yes to this option, support will be included for the
Au1550 and Au1200 SMBus interface.
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 9827c5e..ec42e6c 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -677,19 +677,19 @@ config BLK_DEV_IDE_PMAC_ATA100FIRST
config BLK_DEV_IDE_AU1XXX
bool "IDE for AMD Alchemy Au1200"
- depends on SOC_AU1200
+ depends on MIPS_ALCHEMY
select IDE_XFER_MODE
choice
prompt "IDE Mode for AMD Alchemy Au1200"
default CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
- depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
+ depends on BLK_DEV_IDE_AU1XXX
config BLK_DEV_IDE_AU1XXX_PIO_DBDMA
bool "PIO+DbDMA IDE for AMD Alchemy Au1200"
config BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
bool "MDMA2+DbDMA IDE for AMD Alchemy Au1200"
- depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
+ depends on BLK_DEV_IDE_AU1XXX
endchoice
config BLK_DEV_IDE_TX4938
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 8c87096..6d74f49 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -263,7 +263,7 @@ config MMC_WBSD
config MMC_AU1X
tristate "Alchemy AU1XX0 MMC Card Interface support"
- depends on SOC_AU1200
+ depends on MIPS_ALCHEMY
help
This selects the AMD Alchemy(R) Multimedia card interface.
If you have a Alchemy platform with a MMC slot, say Y or M here.
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4c34252..dbfa0f7 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -138,7 +138,7 @@ config MTD_NAND_RICOH
config MTD_NAND_AU1550
tristate "Au1550/1200 NAND support"
- depends on SOC_AU1200 || SOC_AU1550
+ depends on MIPS_ALCHEMY
help
This enables the driver for the NAND flash controller on the
AMD/Alchemy 1550 SOC.
diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
index 25bb2a0..0cda6c4 100644
--- a/drivers/net/irda/Kconfig
+++ b/drivers/net/irda/Kconfig
@@ -314,7 +314,7 @@ config TOSHIBA_FIR
config AU1000_FIR
tristate "Alchemy Au1000 SIR/FIR"
- depends on SOC_AU1000 && IRDA
+ depends on IRDA && MIPS_ALCHEMY
config SMC_IRCC_FIR
tristate "SMSC IrCC (EXPERIMENTAL)"
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 52e2900..a1fd73d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -88,7 +88,7 @@ config SPI_BFIN_SPORT
config SPI_AU1550
tristate "Au1550/Au12x0 SPI Controller"
- depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL
+ depends on MIPS_ALCHEMY && EXPERIMENTAL
select SPI_BITBANG
help
If you say yes to this option, support will be included for the
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 48f1781..85d5a01 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -56,7 +56,6 @@ config USB_ARCH_HAS_EHCI
boolean
default y if PPC_83xx
default y if PPC_MPC512x
- default y if SOC_AU1200
default y if ARCH_IXP4XX
default y if ARCH_W90X900
default y if ARCH_AT91SAM9G45
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f72ae0b..47aa22d 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1196,7 +1196,7 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ehci_hcd_sh_driver
#endif
-#ifdef CONFIG_SOC_AU1200
+#ifdef CONFIG_MIPS_ALCHEMY
#include "ehci-au1xxx.c"
#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
#endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 549b960..55a7df4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1744,7 +1744,7 @@ endchoice
config FB_AU1100
bool "Au1100 LCD Driver"
- depends on (FB = y) && MIPS && SOC_AU1100
+ depends on (FB = y) && MIPS_ALCHEMY
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1755,7 +1755,7 @@ config FB_AU1100
config FB_AU1200
bool "Au1200 LCD Driver"
- depends on (FB = y) && MIPS && SOC_AU1200
+ depends on (FB = y) && MIPS_ALCHEMY
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
diff --git a/sound/mips/Kconfig b/sound/mips/Kconfig
index a9823fa..0a0d501 100644
--- a/sound/mips/Kconfig
+++ b/sound/mips/Kconfig
@@ -24,7 +24,7 @@ config SND_SGI_HAL2
config SND_AU1X00
tristate "Au1x00 AC97 Port Driver"
- depends on SOC_AU1000 || SOC_AU1100 || SOC_AU1500
+ depends on MIPS_ALCHEMY
select SND_PCM
select SND_AC97_CODEC
help
diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig
index 4b67140..606039f 100644
--- a/sound/soc/au1x/Kconfig
+++ b/sound/soc/au1x/Kconfig
@@ -3,7 +3,7 @@
##
config SND_SOC_AU1XPSC
tristate "SoC Audio for Au1200/Au1250/Au1550"
- depends on SOC_AU1200 || SOC_AU1550
+ depends on MIPS_ALCHEMY
help
This option enables support for the Programmable Serial
Controllers in AC97 and I2S mode, and the Descriptor-Based DMA
--
1.7.6
^ permalink raw reply related [flat|nested] 21+ messages in thread