From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@elte.hu>,
Arnaldo Carvalho de Melo <acme@redhat.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/7] perf, x86: Implement AMD IBS
Date: Tue, 16 Aug 2011 23:05:03 +0200 [thread overview]
Message-ID: <20110816210503.GZ11702@erda.amd.com> (raw)
In-Reply-To: <20110812194344.GJ11702@erda.amd.com>
On 12.08.11 21:43:44, Robert Richter wrote:
> On 02.08.11 07:29:55, Peter Zijlstra wrote:
> > Right, so comparing Fam10 to Fam12,
> >
> > + IbsOpCtl.19:58
> > + IbsOpData.38
> > - IbsOpData2.4:5
>
> Yeah, good catch. This is due to the different northbridge
> implementations. I will ask the hw guys how to handle this.
Both bits are meant to be architectural and defined the same on all
cpus. On families 12h and 14h they always return 0. The documentation
will be updated accordingly.
Thanks,
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
prev parent reply other threads:[~2011-08-16 21:05 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-28 13:46 [PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-07-28 13:46 ` [PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-07-28 13:46 ` [PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:27 ` Robert Richter
2011-08-02 11:49 ` Peter Zijlstra
2011-08-12 17:49 ` Robert Richter
2011-07-28 13:46 ` [PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-08-02 11:35 ` Peter Zijlstra
2011-08-12 19:51 ` Robert Richter
2011-07-28 13:46 ` [PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:32 ` Robert Richter
2011-08-01 15:21 ` Peter Zijlstra
2011-08-01 16:38 ` Don Zickus
2011-08-05 9:55 ` Ingo Molnar
2011-08-05 13:47 ` Don Zickus
2011-08-02 11:43 ` Peter Zijlstra
2011-08-12 18:07 ` Robert Richter
2011-07-28 13:46 ` [PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-07-28 13:46 ` [PATCH 6/7] perf, x86: Example code for AMD IBS Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-08-01 5:50 ` Robert Richter
2011-08-02 10:37 ` Peter Zijlstra
2011-08-03 8:27 ` Michael Cree
2011-08-03 17:56 ` Robert Richter
2011-07-28 13:46 ` [PATCH 7/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-07-29 16:58 ` Peter Zijlstra
2011-07-29 17:02 ` Peter Zijlstra
2011-08-01 5:55 ` Robert Richter
2011-07-29 17:01 ` Peter Zijlstra
2011-08-01 6:13 ` Robert Richter
2011-08-02 11:37 ` Peter Zijlstra
2011-08-12 18:11 ` Robert Richter
2011-07-29 17:07 ` [PATCH 0/7] perf, x86: Implement AMD IBS Peter Zijlstra
2011-08-01 5:21 ` Robert Richter
2011-08-02 11:29 ` Peter Zijlstra
2011-08-12 19:43 ` Robert Richter
2011-08-16 21:05 ` Robert Richter [this message]
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