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From: anarsoul@gmail.com (Vasily Khoruzhick)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] Fix non-LPAE boot regression.
Date: Wed, 24 Aug 2011 11:16:25 +0300	[thread overview]
Message-ID: <201108241116.26118.anarsoul@gmail.com> (raw)
In-Reply-To: <201108151531.45469.anarsoul@gmail.com>

On Monday 15 August 2011 15:31:44 Vasily Khoruzhick wrote:
> On Monday 15 August 2011 15:09:14 Catalin Marinas wrote:
> > Hi Vasily,
> > 
> > On Sat, Aug 13, 2011 at 01:58:19PM +0100, Vasily Khoruzhick wrote:
> > > It was introduced by  407f8b4cb07cbc5c1c7cc386f231224e2524ccea
> > > ARM: LPAE: MMU setup for the 3-level page table format
> > > 
> > > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > > ---
> > > 
> > >  arch/arm/kernel/head.S |    4 ++--
> > >  1 files changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > > index 0bdafc4..5add5f5 100644
> > > --- a/arch/arm/kernel/head.S
> > > +++ b/arch/arm/kernel/head.S
> > > 
> > > @@ -206,7 +206,7 @@ __create_page_tables:
> > >  1:	orr	r3, r7, r5, lsl #SECTION_SHIFT	@ flags + kernel base
> > >  
> > >  	str	r3, [r4, r5, lsl #PMD_ORDER]	@ identity mapping
> > >  	cmp	r5, r6
> > > 
> > > -	addlo	r5, r5, #SECTION_SHIFT >> 20	@ next section
> > > +	addlo	r5, r5, #1			@ next section
> > > 
> > >  	blo	1b
> > 
> > That's correct.
> > 
> > >  	/*
> > > 
> > > @@ -217,7 +217,7 @@ __create_page_tables:
> > >  	mov	r3, r3, lsr #SECTION_SHIFT
> > >  	orr	r3, r7, r3, lsl #SECTION_SHIFT
> > >  	add	r0, r4,  #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT -
> > >  	PMD_ORDER)
> > > 
> > > -	str	r3, [r0, #(KERNEL_START & 0x00e00000) >> (SECTION_SHIFT -
> > > PMD_ORDER)]! +	str	r3, [r0, #(KERNEL_START & 0x00f00000) >>
> > > (SECTION_SHIFT - PMD_ORDER)]!
> > 
> > The reason for this was that the sections are 2MB with LPAE and a page
> > table entry is 64-bit wide. We always shift that value by 18 but with
> > LPAE we don't want to write in the middle of a page table entry if
> > KERNEL_START is not 2MB aligned.
> > 
> > But if KERNEL_START is not 2MB aligned, I think we get the wrong
> > physical address by 1MB (with the classic page table format).
> 
> Yep, for my case KERNEL_START is not 2MB aligned (TEXT_OFFSET is 0x00108000). 
> (CONFIG_PM_H1940 is set)
> 
> > There are a few alternatives to fixing this:
> > 
> > 1. Different KERNEL_START masking for classic or LPAE page tables.
> > 2. Always force 2MB section and the code above moving the phys addr into
> >    r3 would need to take this into account.
> > 
> > I would go for 1 with some shifting like below:
> > 
> > +	str	r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) <<
> > PMD_ORDER]!
> > 
> > This should give us 0x00f00000 with classic page tables and 0x00e00000
> > with LPAE.
> > 
> > Thanks.
> 
> Ok, I'll test this change when I get home.

Works for me on s3c24xx. Sorry for a delay.

Regards
Vasily

WARNING: multiple messages have this Message-ID (diff)
From: Vasily Khoruzhick <anarsoul@gmail.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"Russell King - ARM Linux" <linux@arm.linux.org.uk>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] Fix non-LPAE boot regression.
Date: Wed, 24 Aug 2011 11:16:25 +0300	[thread overview]
Message-ID: <201108241116.26118.anarsoul@gmail.com> (raw)
In-Reply-To: <201108151531.45469.anarsoul@gmail.com>

On Monday 15 August 2011 15:31:44 Vasily Khoruzhick wrote:
> On Monday 15 August 2011 15:09:14 Catalin Marinas wrote:
> > Hi Vasily,
> > 
> > On Sat, Aug 13, 2011 at 01:58:19PM +0100, Vasily Khoruzhick wrote:
> > > It was introduced by  407f8b4cb07cbc5c1c7cc386f231224e2524ccea
> > > ARM: LPAE: MMU setup for the 3-level page table format
> > > 
> > > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > > ---
> > > 
> > >  arch/arm/kernel/head.S |    4 ++--
> > >  1 files changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
> > > index 0bdafc4..5add5f5 100644
> > > --- a/arch/arm/kernel/head.S
> > > +++ b/arch/arm/kernel/head.S
> > > 
> > > @@ -206,7 +206,7 @@ __create_page_tables:
> > >  1:	orr	r3, r7, r5, lsl #SECTION_SHIFT	@ flags + kernel base
> > >  
> > >  	str	r3, [r4, r5, lsl #PMD_ORDER]	@ identity mapping
> > >  	cmp	r5, r6
> > > 
> > > -	addlo	r5, r5, #SECTION_SHIFT >> 20	@ next section
> > > +	addlo	r5, r5, #1			@ next section
> > > 
> > >  	blo	1b
> > 
> > That's correct.
> > 
> > >  	/*
> > > 
> > > @@ -217,7 +217,7 @@ __create_page_tables:
> > >  	mov	r3, r3, lsr #SECTION_SHIFT
> > >  	orr	r3, r7, r3, lsl #SECTION_SHIFT
> > >  	add	r0, r4,  #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT -
> > >  	PMD_ORDER)
> > > 
> > > -	str	r3, [r0, #(KERNEL_START & 0x00e00000) >> (SECTION_SHIFT -
> > > PMD_ORDER)]! +	str	r3, [r0, #(KERNEL_START & 0x00f00000) >>
> > > (SECTION_SHIFT - PMD_ORDER)]!
> > 
> > The reason for this was that the sections are 2MB with LPAE and a page
> > table entry is 64-bit wide. We always shift that value by 18 but with
> > LPAE we don't want to write in the middle of a page table entry if
> > KERNEL_START is not 2MB aligned.
> > 
> > But if KERNEL_START is not 2MB aligned, I think we get the wrong
> > physical address by 1MB (with the classic page table format).
> 
> Yep, for my case KERNEL_START is not 2MB aligned (TEXT_OFFSET is 0x00108000). 
> (CONFIG_PM_H1940 is set)
> 
> > There are a few alternatives to fixing this:
> > 
> > 1. Different KERNEL_START masking for classic or LPAE page tables.
> > 2. Always force 2MB section and the code above moving the phys addr into
> >    r3 would need to take this into account.
> > 
> > I would go for 1 with some shifting like below:
> > 
> > +	str	r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) <<
> > PMD_ORDER]!
> > 
> > This should give us 0x00f00000 with classic page tables and 0x00e00000
> > with LPAE.
> > 
> > Thanks.
> 
> Ok, I'll test this change when I get home.

Works for me on s3c24xx. Sorry for a delay.

Regards
Vasily

  reply	other threads:[~2011-08-24  8:16 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-10 15:03 [PATCH v7 00/16] ARM: Add support for the Large Physical Address Extensions Catalin Marinas
2011-08-10 15:03 ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 01/16] ARM: LPAE: add ISBs around MMU enabling code Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 02/16] ARM: LPAE: Cast the dma_addr_t argument to unsigned long in dma_to_virt Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-13 14:33   ` Russell King - ARM Linux
2011-08-13 14:33     ` Russell King - ARM Linux
2011-08-23 11:15     ` Russell King - ARM Linux
2011-08-23 11:15       ` Russell King - ARM Linux
2011-08-10 15:03 ` [PATCH v7 03/16] ARM: LPAE: Use PMD_(SHIFT|SIZE|MASK) instead of PGDIR_* Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-13 14:34   ` Russell King - ARM Linux
2011-08-13 14:34     ` Russell King - ARM Linux
2011-08-15 16:48   ` Catalin Marinas
2011-08-15 16:48     ` Catalin Marinas
2011-08-23 11:15   ` Russell King - ARM Linux
2011-08-23 11:15     ` Russell King - ARM Linux
2011-08-23 13:09     ` Catalin Marinas
2011-08-23 13:09       ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 04/16] ARM: LPAE: Factor out 2-level page table definitions into separate files Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 05/16] ARM: LPAE: Add (pte|pmd)val_t type definitions as u32 Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 06/16] ARM: LPAE: Use a mask for physical addresses in page table entries Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 07/16] ARM: LPAE: Introduce the 3-level page table format definitions Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 08/16] ARM: LPAE: Page table maintenance for the 3-level format Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-10-23 11:56   ` Russell King - ARM Linux
2011-10-23 11:56     ` Russell King - ARM Linux
2011-10-23 12:49     ` Catalin Marinas
2011-10-23 12:49       ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 09/16] ARM: LPAE: MMU setup for the 3-level page table format Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-13 11:49   ` Vasily Khoruzhick
2011-08-13 11:49     ` Vasily Khoruzhick
2011-08-13 12:56   ` Vasily Khoruzhick
2011-08-13 12:56     ` Vasily Khoruzhick
2011-08-13 12:58     ` [PATCH] Fix non-LPAE boot regression Vasily Khoruzhick
2011-08-13 12:58       ` Vasily Khoruzhick
2011-08-13 14:14       ` Catalin Marinas
2011-08-13 14:14         ` Catalin Marinas
2011-08-13 14:39         ` Russell King - ARM Linux
2011-08-13 14:39           ` Russell King - ARM Linux
2011-08-13 14:45           ` Catalin Marinas
2011-08-13 14:45             ` Catalin Marinas
2011-08-15 11:41           ` Catalin Marinas
2011-08-15 11:41             ` Catalin Marinas
2011-08-15 12:09       ` Catalin Marinas
2011-08-15 12:09         ` Catalin Marinas
2011-08-15 12:31         ` Vasily Khoruzhick
2011-08-15 12:31           ` Vasily Khoruzhick
2011-08-24  8:16           ` Vasily Khoruzhick [this message]
2011-08-24  8:16             ` Vasily Khoruzhick
2011-08-15 16:51   ` [PATCH v7 09/16] ARM: LPAE: MMU setup for the 3-level page table format Catalin Marinas
2011-08-15 16:51     ` Catalin Marinas
2011-08-19 10:25   ` Ian Campbell
2011-08-19 10:25     ` Ian Campbell
2011-08-19 11:10     ` Catalin Marinas
2011-08-19 11:10       ` Catalin Marinas
2011-08-19 11:47       ` Ian Campbell
2011-08-19 11:47         ` Ian Campbell
2011-08-10 15:03 ` [PATCH v7 10/16] ARM: LPAE: Invalidate the TLB before freeing the PMD Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 11/16] ARM: LPAE: Add fault handling support Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-10-23 11:57   ` Russell King - ARM Linux
2011-10-23 11:57     ` Russell King - ARM Linux
2011-11-02 17:02     ` Catalin Marinas
2011-11-02 17:02       ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 12/16] ARM: LPAE: Add context switching support Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 13/16] ARM: LPAE: Add identity mapping support for the 3-level page table format Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-10-23 11:59   ` Russell King - ARM Linux
2011-10-23 11:59     ` Russell King - ARM Linux
2011-08-10 15:03 ` [PATCH v7 14/16] ARM: LPAE: mark memory banks with start > ULONG_MAX as highmem Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-08-10 15:03 ` [PATCH v7 15/16] ARM: LPAE: add support for ATAG_MEM64 Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-10-23 11:59   ` Russell King - ARM Linux
2011-10-23 11:59     ` Russell King - ARM Linux
2011-08-10 15:03 ` [PATCH v7 16/16] ARM: LPAE: Add the Kconfig entries Catalin Marinas
2011-08-10 15:03   ` Catalin Marinas
2011-10-23 12:00   ` Russell King - ARM Linux
2011-10-23 12:00     ` Russell King - ARM Linux
2011-11-02 17:21   ` Russell King - ARM Linux
2011-11-02 17:21     ` Russell King - ARM Linux
2011-11-02 18:07     ` Catalin Marinas
2011-11-02 18:07       ` Catalin Marinas

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