All of lore.kernel.org
 help / color / mirror / Atom feed
From: gbean@codeaurora.org (Gregory Bean)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/4 v4] drivers: create a pin control subsystem
Date: Thu, 25 Aug 2011 11:14:04 -0700	[thread overview]
Message-ID: <20110825181404.GA19345@gbean-linux.qualcomm.com> (raw)
In-Reply-To: <20110825151210.GC31331@huya.qualcomm.com>

On Thu, Aug 25, 2011 at 08:12:10AM -0700, David Brown wrote:
> On Thu, Aug 25, 2011 at 12:12:59PM +0200, Linus Walleij wrote:
> 
> > mach-msm:
> > ----------------
> > 
> > Hard to tell how this works and what's available, support
> > seems to be incomplete. Currently it seems to be wired
> > to do either a dedicated function (like some UART pin)
> > or GPIO, like each pin can be used for two specific
> > things, and not phone-exchange type.
> 
> There are some pins on MSMs that can be connected to different hw
> blocks, we just haven't gotten the support into the kernel yet.
> 
> There are some things where two devices share pins, and you have to
> choose one or the other.
> 
> I believe there are also configurations where something such as the SD
> controller can either be configured in 8-bit data mode, or in 4-bit
> data mode, and those 4 pins connected to something else.
> 
> Much of the current pin configuration in our product kernel seems to
> be about current and pull up/down configuration.
> 
> I've added Rohit Vaswani, and Greg Bean to this thread who should have
> a bit better understanding of this.

The MSM pinmux system allows every pin to be independently controlled
in the following ways:

- function selection:  Every pin can be in GPIO mode, or connected to
  a specific piece of hardware.  The number of choices varies by pin -
  some pins have only two choices, some have eight.  When a pin is not in
  GPIO mode, it loses some configurability - for instance, its direction
  can no longer be set, as that's predetermined by the function selection.
  Pins can belong to many groups which overlap in all kinds of interesting
  ways - a pin may be part of this four-bit bus, or that eight-bit bus, or
  might stand alone for two settings...

- drive strength: Each pin can be set to have a different drive strength
  between 2MA and 16MA, in 2MA steps.

- pull settings: Each pin can be configured with a variety of pull
  settings: up, down, keeper, no pull.

Additionally, there are complexities involving delivering
interrupts from GPIOs:

- 'direct-connect' or 'summary' interrupts: pins which are being used as
  interrupt inputs can be 'summarized' through a single interrupt
  (requiring an additional pile of register reads to figure out which
  gpio triggered the interrupt) or as a 'direct-connect' interrupt.
  There are very few direct-connect lines available, so most gpio
  interrupts are summarized.

- processor interrupt assignment: Each pin can be assigned to deliver
  interrupts to a different processor on the board.  This pin might be
  assigned to the MSM, that pin might go to the DSP, the next might
  go to the modem, and so on...

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

WARNING: multiple messages have this Message-ID (diff)
From: Gregory Bean <gbean@codeaurora.org>
To: David Brown <davidb@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>,
	rvaswani@codeaurora.org, Stephen Warren <swarren@nvidia.com>,
	Linus Walleij <linus.walleij@stericsson.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Grant Likely <grant.likely@secretlab.ca>,
	Lee Jones <lee.jones@linaro.org>, Joe Perches <joe@perches.com>,
	Russell King <linux@arm.linux.org.uk>,
	Linaro Dev <linaro-dev@lists.linaro.org>,
	ext Tony Lindgren <tony@atomide.com>,
	Sascha Hauer <kernel@pengutronix.de>
Subject: Re: [PATCH 1/4 v4] drivers: create a pin control subsystem
Date: Thu, 25 Aug 2011 11:14:04 -0700	[thread overview]
Message-ID: <20110825181404.GA19345@gbean-linux.qualcomm.com> (raw)
In-Reply-To: <20110825151210.GC31331@huya.qualcomm.com>

On Thu, Aug 25, 2011 at 08:12:10AM -0700, David Brown wrote:
> On Thu, Aug 25, 2011 at 12:12:59PM +0200, Linus Walleij wrote:
> 
> > mach-msm:
> > ----------------
> > 
> > Hard to tell how this works and what's available, support
> > seems to be incomplete. Currently it seems to be wired
> > to do either a dedicated function (like some UART pin)
> > or GPIO, like each pin can be used for two specific
> > things, and not phone-exchange type.
> 
> There are some pins on MSMs that can be connected to different hw
> blocks, we just haven't gotten the support into the kernel yet.
> 
> There are some things where two devices share pins, and you have to
> choose one or the other.
> 
> I believe there are also configurations where something such as the SD
> controller can either be configured in 8-bit data mode, or in 4-bit
> data mode, and those 4 pins connected to something else.
> 
> Much of the current pin configuration in our product kernel seems to
> be about current and pull up/down configuration.
> 
> I've added Rohit Vaswani, and Greg Bean to this thread who should have
> a bit better understanding of this.

The MSM pinmux system allows every pin to be independently controlled
in the following ways:

- function selection:  Every pin can be in GPIO mode, or connected to
  a specific piece of hardware.  The number of choices varies by pin -
  some pins have only two choices, some have eight.  When a pin is not in
  GPIO mode, it loses some configurability - for instance, its direction
  can no longer be set, as that's predetermined by the function selection.
  Pins can belong to many groups which overlap in all kinds of interesting
  ways - a pin may be part of this four-bit bus, or that eight-bit bus, or
  might stand alone for two settings...

- drive strength: Each pin can be set to have a different drive strength
  between 2MA and 16MA, in 2MA steps.

- pull settings: Each pin can be configured with a variety of pull
  settings: up, down, keeper, no pull.

Additionally, there are complexities involving delivering
interrupts from GPIOs:

- 'direct-connect' or 'summary' interrupts: pins which are being used as
  interrupt inputs can be 'summarized' through a single interrupt
  (requiring an additional pile of register reads to figure out which
  gpio triggered the interrupt) or as a 'direct-connect' interrupt.
  There are very few direct-connect lines available, so most gpio
  interrupts are summarized.

- processor interrupt assignment: Each pin can be assigned to deliver
  interrupts to a different processor on the board.  This pin might be
  assigned to the MSM, that pin might go to the DSP, the next might
  go to the modem, and so on...

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

  reply	other threads:[~2011-08-25 18:14 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-19  9:53 [PATCH 1/4 v4] drivers: create a pin control subsystem Linus Walleij
2011-08-19  9:53 ` Linus Walleij
2011-08-19 10:48 ` Jamie Iles
2011-08-19 10:48   ` Jamie Iles
2011-08-19 14:04   ` Linus Walleij
2011-08-19 14:04     ` Linus Walleij
2011-08-19 14:26     ` Jamie Iles
2011-08-19 14:26       ` Jamie Iles
2011-08-21 14:24       ` Jamie Iles
2011-08-21 14:24         ` Jamie Iles
2011-08-22 12:38         ` Linus Walleij
2011-08-22 12:38           ` Linus Walleij
2011-08-22 12:54           ` Jamie Iles
2011-08-22 12:54             ` Jamie Iles
2011-08-19 14:36     ` Arnd Bergmann
2011-08-19 14:36       ` Arnd Bergmann
2011-08-19 16:52       ` Greg KH
2011-08-19 16:52         ` Greg KH
2011-08-22 12:29         ` Linus Walleij
2011-08-22 12:29           ` Linus Walleij
2011-08-21 14:53 ` Barry Song
2011-08-21 14:53   ` Barry Song
2011-08-24  6:24 ` Barry Song
2011-08-24  6:24   ` Barry Song
2011-08-24  7:41   ` Linus Walleij
2011-08-24  7:41     ` Linus Walleij
2011-08-24 18:29 ` Stephen Warren
2011-08-24 18:29   ` Stephen Warren
2011-08-25 10:12   ` Linus Walleij
2011-08-25 10:12     ` Linus Walleij
2011-08-25 11:04     ` Sascha Hauer
2011-08-25 11:04       ` Sascha Hauer
2011-08-25 11:58       ` Linus Walleij
2011-08-25 11:58         ` Linus Walleij
2011-08-25 12:07         ` Sascha Hauer
2011-08-25 12:07           ` Sascha Hauer
2011-08-25 15:12     ` David Brown
2011-08-25 15:12       ` David Brown
2011-08-25 18:14       ` Gregory Bean [this message]
2011-08-25 18:14         ` Gregory Bean
2011-08-25 19:13     ` Stephen Warren
2011-08-25 19:13       ` Stephen Warren
2011-08-26  8:35       ` Linus Walleij
2011-08-26  8:35         ` Linus Walleij
2011-08-26 17:33         ` Stephen Warren
2011-08-26 17:33           ` Stephen Warren
2011-08-29  8:40           ` Linus Walleij
2011-08-29  8:40             ` Linus Walleij
2011-08-26  3:12 ` Barry Song
2011-08-26  3:12   ` Barry Song
2011-08-26  8:36   ` Linus Walleij
2011-08-26  8:36     ` Linus Walleij
2011-09-02  7:02 ` Stijn Devriendt
2011-09-02  7:02   ` Stijn Devriendt
2011-09-02  7:57   ` Linus Walleij
2011-09-02  7:57     ` Linus Walleij

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20110825181404.GA19345@gbean-linux.qualcomm.com \
    --to=gbean@codeaurora.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.