[PATCH 0/4] Support for PRI and PASID capability

[PATCH 0/4] Support for PRI and PASID capability

[Joerg Roedel]

Hi Jesse,

here is a patch-set that enables support for the PRI and PASID
capabilities in the Linux PCI core. These capabilities of a PCIe device
are tightly coupled with ATS, but not with IOV. So these patches start
by moving the ATS code into its own file: ats.c.

Support for the other two capabilities is based on that change. Please
review the patches and let me know of any objections you might have.

Thanks,

	Joerg

Diffstat:

 drivers/pci/Kconfig      |   24 +++
 drivers/pci/Makefile     |    1 +
 drivers/pci/ats.c        |  438 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/iov.c        |  142 ---------------
 include/linux/pci-ats.h  |   75 ++++++++
 include/linux/pci_regs.h |   20 ++
 6 files changed, 558 insertions(+), 142 deletions(-)

[PATCH 1/4] PCI: Move ATS implementation into own file

[Joerg Roedel]

ATS does not depend on IOV support, so move the code into
its own file. This file will also include support for the
PRI and PASID capability later.
Also give ATS its own Kconfig variable to allow selecting it
without IOV support.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 drivers/pci/Kconfig     |    4 +
 drivers/pci/Makefile    |    1 +
 drivers/pci/ats.c       |  155 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/iov.c       |  142 -------------------------------------------
 include/linux/pci-ats.h |    2 +
 5 files changed, 162 insertions(+), 142 deletions(-)
 create mode 100644 drivers/pci/ats.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 0fa466a..1d8ce83 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -71,9 +71,13 @@ config HT_IRQ
 
 	   If unsure say Y.
 
+config PCI_ATS
+	bool
+
 config PCI_IOV
 	bool "PCI IOV support"
 	depends on PCI
+	select PCI_ATS
 	help
 	  I/O Virtualization is a PCI feature supported by some devices
 	  which allows them to create virtual devices which share their
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 6fadae3..083a49f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_PCI_MSI) += msi.o
 # Build the Hypertransport interrupt support
 obj-$(CONFIG_HT_IRQ) += htirq.o
 
+obj-$(CONFIG_PCI_ATS) += ats.o
 obj-$(CONFIG_PCI_IOV) += iov.o
 
 #
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
new file mode 100644
index 0000000..ae4bf87
--- /dev/null
+++ b/drivers/pci/ats.c
@@ -0,0 +1,155 @@
+/*
+ * drivers/pci/ats.c
+ *
+ * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
+ *
+ * PCI Express I/O Virtualization (IOV) support.
+ *   Address Translation Service 1.0
+ */
+
+#include <linux/pci-ats.h>
+#include <linux/pci.h>
+
+#include "pci.h"
+
+static int ats_alloc_one(struct pci_dev *dev, int ps)
+{
+	int pos;
+	u16 cap;
+	struct pci_ats *ats;
+
+	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
+	if (!pos)
+		return -ENODEV;
+
+	ats = kzalloc(sizeof(*ats), GFP_KERNEL);
+	if (!ats)
+		return -ENOMEM;
+
+	ats->pos = pos;
+	ats->stu = ps;
+	pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
+	ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
+					    PCI_ATS_MAX_QDEP;
+	dev->ats = ats;
+
+	return 0;
+}
+
+static void ats_free_one(struct pci_dev *dev)
+{
+	kfree(dev->ats);
+	dev->ats = NULL;
+}
+
+/**
+ * pci_enable_ats - enable the ATS capability
+ * @dev: the PCI device
+ * @ps: the IOMMU page shift
+ *
+ * Returns 0 on success, or negative on failure.
+ */
+int pci_enable_ats(struct pci_dev *dev, int ps)
+{
+	int rc;
+	u16 ctrl;
+
+	BUG_ON(dev->ats && dev->ats->is_enabled);
+
+	if (ps < PCI_ATS_MIN_STU)
+		return -EINVAL;
+
+	if (dev->is_physfn || dev->is_virtfn) {
+		struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
+
+		mutex_lock(&pdev->sriov->lock);
+		if (pdev->ats)
+			rc = pdev->ats->stu == ps ? 0 : -EINVAL;
+		else
+			rc = ats_alloc_one(pdev, ps);
+
+		if (!rc)
+			pdev->ats->ref_cnt++;
+		mutex_unlock(&pdev->sriov->lock);
+		if (rc)
+			return rc;
+	}
+
+	if (!dev->is_physfn) {
+		rc = ats_alloc_one(dev, ps);
+		if (rc)
+			return rc;
+	}
+
+	ctrl = PCI_ATS_CTRL_ENABLE;
+	if (!dev->is_virtfn)
+		ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
+	pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
+
+	dev->ats->is_enabled = 1;
+
+	return 0;
+}
+
+/**
+ * pci_disable_ats - disable the ATS capability
+ * @dev: the PCI device
+ */
+void pci_disable_ats(struct pci_dev *dev)
+{
+	u16 ctrl;
+
+	BUG_ON(!dev->ats || !dev->ats->is_enabled);
+
+	pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
+	ctrl &= ~PCI_ATS_CTRL_ENABLE;
+	pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
+
+	dev->ats->is_enabled = 0;
+
+	if (dev->is_physfn || dev->is_virtfn) {
+		struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
+
+		mutex_lock(&pdev->sriov->lock);
+		pdev->ats->ref_cnt--;
+		if (!pdev->ats->ref_cnt)
+			ats_free_one(pdev);
+		mutex_unlock(&pdev->sriov->lock);
+	}
+
+	if (!dev->is_physfn)
+		ats_free_one(dev);
+}
+
+/**
+ * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
+ * @dev: the PCI device
+ *
+ * Returns the queue depth on success, or negative on failure.
+ *
+ * The ATS spec uses 0 in the Invalidate Queue Depth field to
+ * indicate that the function can accept 32 Invalidate Request.
+ * But here we use the `real' values (i.e. 1~32) for the Queue
+ * Depth; and 0 indicates the function shares the Queue with
+ * other functions (doesn't exclusively own a Queue).
+ */
+int pci_ats_queue_depth(struct pci_dev *dev)
+{
+	int pos;
+	u16 cap;
+
+	if (dev->is_virtfn)
+		return 0;
+
+	if (dev->ats)
+		return dev->ats->qdep;
+
+	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
+	if (!pos)
+		return -ENODEV;
+
+	pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
+
+	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
+				       PCI_ATS_MAX_QDEP;
+}
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 42fae47..9b4e88c 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -722,145 +722,3 @@ int pci_num_vf(struct pci_dev *dev)
 		return dev->sriov->nr_virtfn;
 }
 EXPORT_SYMBOL_GPL(pci_num_vf);
-
-static int ats_alloc_one(struct pci_dev *dev, int ps)
-{
-	int pos;
-	u16 cap;
-	struct pci_ats *ats;
-
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
-	if (!pos)
-		return -ENODEV;
-
-	ats = kzalloc(sizeof(*ats), GFP_KERNEL);
-	if (!ats)
-		return -ENOMEM;
-
-	ats->pos = pos;
-	ats->stu = ps;
-	pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
-	ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
-					    PCI_ATS_MAX_QDEP;
-	dev->ats = ats;
-
-	return 0;
-}
-
-static void ats_free_one(struct pci_dev *dev)
-{
-	kfree(dev->ats);
-	dev->ats = NULL;
-}
-
-/**
- * pci_enable_ats - enable the ATS capability
- * @dev: the PCI device
- * @ps: the IOMMU page shift
- *
- * Returns 0 on success, or negative on failure.
- */
-int pci_enable_ats(struct pci_dev *dev, int ps)
-{
-	int rc;
-	u16 ctrl;
-
-	BUG_ON(dev->ats && dev->ats->is_enabled);
-
-	if (ps < PCI_ATS_MIN_STU)
-		return -EINVAL;
-
-	if (dev->is_physfn || dev->is_virtfn) {
-		struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
-
-		mutex_lock(&pdev->sriov->lock);
-		if (pdev->ats)
-			rc = pdev->ats->stu == ps ? 0 : -EINVAL;
-		else
-			rc = ats_alloc_one(pdev, ps);
-
-		if (!rc)
-			pdev->ats->ref_cnt++;
-		mutex_unlock(&pdev->sriov->lock);
-		if (rc)
-			return rc;
-	}
-
-	if (!dev->is_physfn) {
-		rc = ats_alloc_one(dev, ps);
-		if (rc)
-			return rc;
-	}
-
-	ctrl = PCI_ATS_CTRL_ENABLE;
-	if (!dev->is_virtfn)
-		ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
-	pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
-
-	dev->ats->is_enabled = 1;
-
-	return 0;
-}
-
-/**
- * pci_disable_ats - disable the ATS capability
- * @dev: the PCI device
- */
-void pci_disable_ats(struct pci_dev *dev)
-{
-	u16 ctrl;
-
-	BUG_ON(!dev->ats || !dev->ats->is_enabled);
-
-	pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
-	ctrl &= ~PCI_ATS_CTRL_ENABLE;
-	pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
-
-	dev->ats->is_enabled = 0;
-
-	if (dev->is_physfn || dev->is_virtfn) {
-		struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
-
-		mutex_lock(&pdev->sriov->lock);
-		pdev->ats->ref_cnt--;
-		if (!pdev->ats->ref_cnt)
-			ats_free_one(pdev);
-		mutex_unlock(&pdev->sriov->lock);
-	}
-
-	if (!dev->is_physfn)
-		ats_free_one(dev);
-}
-
-/**
- * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
- * @dev: the PCI device
- *
- * Returns the queue depth on success, or negative on failure.
- *
- * The ATS spec uses 0 in the Invalidate Queue Depth field to
- * indicate that the function can accept 32 Invalidate Request.
- * But here we use the `real' values (i.e. 1~32) for the Queue
- * Depth; and 0 indicates the function shares the Queue with
- * other functions (doesn't exclusively own a Queue).
- */
-int pci_ats_queue_depth(struct pci_dev *dev)
-{
-	int pos;
-	u16 cap;
-
-	if (dev->is_virtfn)
-		return 0;
-
-	if (dev->ats)
-		return dev->ats->qdep;
-
-	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
-	if (!pos)
-		return -ENODEV;
-
-	pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
-
-	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
-				       PCI_ATS_MAX_QDEP;
-}
diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index 655824f..4eab42b 100644
--- a/include/linux/pci-ats.h
+++ b/include/linux/pci-ats.h
@@ -1,6 +1,8 @@
 #ifndef LINUX_PCI_ATS_H
 #define LINUX_PCI_ATS_H
 
+#include <linux/pci.h>
+
 /* Address Translation Service */
 struct pci_ats {
 	int pos;        /* capability position */
-- 
1.7.4.1

[PATCH 2/4] PCI: Export ATS functions to modules

[Joerg Roedel]

This patch makes the ATS function usable for modules. This
will be used by a modules implementing some advanced
AMD IOMMU features.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 drivers/pci/ats.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index ae4bf87..5ceff3e 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -90,6 +90,7 @@ int pci_enable_ats(struct pci_dev *dev, int ps)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(pci_enable_ats);
 
 /**
  * pci_disable_ats - disable the ATS capability
@@ -120,6 +121,7 @@ void pci_disable_ats(struct pci_dev *dev)
 	if (!dev->is_physfn)
 		ats_free_one(dev);
 }
+EXPORT_SYMBOL_GPL(pci_disable_ats);
 
 /**
  * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
@@ -153,3 +155,4 @@ int pci_ats_queue_depth(struct pci_dev *dev)
 	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
 				       PCI_ATS_MAX_QDEP;
 }
+EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
-- 
1.7.4.1

[PATCH 3/4] PCI: Add implementation for PRI capability

[Joerg Roedel]

Implement the necessary functions to handle PRI capabilities
on PCIe devices. With PRI devices behind an IOMMU can signal
page fault conditions to software and recover from such
faults.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 drivers/pci/Kconfig      |    9 +++
 drivers/pci/ats.c        |  167 ++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/pci-ats.h  |   42 ++++++++++++
 include/linux/pci_regs.h |   12 +++
 4 files changed, 230 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 1d8ce83..fb1e9707 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -85,6 +85,15 @@ config PCI_IOV
 
 	  If unsure, say N.
 
+config PCI_PRI
+	bool "PCI PRI support"
+	select PCI_ATS
+	help
+	  PRI is the PCI Page Request Interface. It allows PCI devices that are
+	  behind an IOMMU to recover from page faults.
+
+	  If unsure, say N.
+
 config PCI_IOAPIC
 	bool
 	depends on PCI
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index 5ceff3e..bf892a0 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -2,9 +2,11 @@
  * drivers/pci/ats.c
  *
  * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
+ * Copyright (C) 2011 Advanced Micro Devices,
  *
  * PCI Express I/O Virtualization (IOV) support.
  *   Address Translation Service 1.0
+ *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
  */
 
 #include <linux/pci-ats.h>
@@ -156,3 +158,168 @@ int pci_ats_queue_depth(struct pci_dev *dev)
 				       PCI_ATS_MAX_QDEP;
 }
 EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
+
+#ifdef CONFIG_PCI_PRI
+/**
+ * pci_enable_pri - Enable PRI capability
+ * @ pdev: PCI device structure
+ *
+ * Returns 0 on success, negative value on error
+ */
+int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
+{
+	u16 control, status;
+	u32 max_requests;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+	pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF,  &status);
+	if ((control & PCI_PRI_ENABLE) || !(status & PCI_PRI_STATUS_STOPPED))
+		return -EBUSY;
+
+	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ_OFF, &max_requests);
+	reqs = min(max_requests, reqs);
+	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ_OFF, reqs);
+
+	control |= PCI_PRI_ENABLE;
+	pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pci_enable_pri);
+
+/**
+ * pci_disable_pri - Disable PRI capability
+ * @pdev: PCI device structure
+ *
+ * Only clears the enabled-bit, regardless of its former value
+ */
+void pci_disable_pri(struct pci_dev *pdev)
+{
+	u16 control;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+	if (!pos)
+		return;
+
+	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+	control &= ~PCI_PRI_ENABLE;
+	pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+}
+EXPORT_SYMBOL_GPL(pci_disable_pri);
+
+/**
+ * pci_pri_enabled - Checks if PRI capability is enabled
+ * @pdev: PCI device structure
+ *
+ * Returns true if PRI is enabled on the device, false otherwise
+ */
+bool pci_pri_enabled(struct pci_dev *pdev)
+{
+	u16 control;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+	if (!pos)
+		return false;
+
+	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+
+	return (control & PCI_PRI_ENABLE) ? true : false;
+}
+EXPORT_SYMBOL_GPL(pci_pri_enabled);
+
+/**
+ * pci_reset_pri - Resets device's PRI state
+ * @pdev: PCI device structure
+ *
+ * The PRI capability must be disabled before this function is called.
+ * Returns 0 on success, negative value on error.
+ */
+int pci_reset_pri(struct pci_dev *pdev)
+{
+	u16 control;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+	if (control & PCI_PRI_ENABLE)
+		return -EBUSY;
+
+	control |= PCI_PRI_RESET;
+
+	pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pci_reset_pri);
+
+/**
+ * pci_pri_stopped - Checks whether the PRI capability is stopped
+ * @pdev: PCI device structure
+ *
+ * Returns true if the PRI capability on the device is disabled and the
+ * device has no outstanding PRI requests, false otherwise. The device
+ * indicates this via the STOPPED bit in the status register of the
+ * capability.
+ * The device internal state can be cleared by resetting the PRI state
+ * with pci_reset_pri(). This can force the capability into the STOPPED
+ * state.
+ */
+bool pci_pri_stopped(struct pci_dev *pdev)
+{
+	u16 control, status;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+	if (!pos)
+		return true;
+
+	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+	pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF,  &status);
+
+	if (control & PCI_PRI_ENABLE)
+		return false;
+
+	return (status & PCI_PRI_STATUS_STOPPED) ? true : false;
+}
+EXPORT_SYMBOL_GPL(pci_pri_stopped);
+
+/**
+ * pci_pri_status - Request PRI status of a device
+ * @pdev: PCI device structure
+ *
+ * Returns negative value on failure, status on success. The status can
+ * be checked against status-bits. Supported bits are currently:
+ * PCI_PRI_STATUS_RF:      Response failure
+ * PCI_PRI_STATUS_UPRGI:   Unexpected Page Request Group Index
+ * PCI_PRI_STATUS_STOPPED: PRI has stopped
+ */
+int pci_pri_status(struct pci_dev *pdev)
+{
+	u16 status, control;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+	pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF,  &status);
+
+	/* Stopped bit is undefined when enable == 1, so clear it */
+	if (control & PCI_PRI_ENABLE)
+		status &= ~PCI_PRI_STATUS_STOPPED;
+
+	return status;
+}
+EXPORT_SYMBOL_GPL(pci_pri_status);
+#endif /* CONFIG_PCI_PRI */
diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index 4eab42b..0713952 100644
--- a/include/linux/pci-ats.h
+++ b/include/linux/pci-ats.h
@@ -17,6 +17,7 @@ struct pci_ats {
 extern int pci_enable_ats(struct pci_dev *dev, int ps);
 extern void pci_disable_ats(struct pci_dev *dev);
 extern int pci_ats_queue_depth(struct pci_dev *dev);
+
 /**
  * pci_ats_enabled - query the ATS status
  * @dev: the PCI device
@@ -51,4 +52,45 @@ static inline int pci_ats_enabled(struct pci_dev *dev)
 
 #endif /* CONFIG_PCI_IOV */
 
+#ifdef CONFIG_PCI_PRI
+
+extern int  pci_enable_pri(struct pci_dev *pdev, u32 reqs);
+extern void pci_disable_pri(struct pci_dev *pdev);
+extern bool pci_pri_enabled(struct pci_dev *pdev);
+extern int  pci_reset_pri(struct pci_dev *pdev);
+extern bool pci_pri_stopped(struct pci_dev *pdev);
+extern int  pci_pri_status(struct pci_dev *pdev);
+
+#else /* CONFIG_PCI_PRI */
+
+static inline int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
+{
+	return -ENODEV;
+}
+
+static inline void pci_disable_pri(struct pci_dev *pdev)
+{
+}
+
+static inline bool pci_pri_enabled(struct pci_dev *pdev)
+{
+	return false;
+}
+
+static inline int pci_reset_pri(struct pci_dev *pdev)
+{
+	return -ENODEV;
+}
+
+static inline bool pci_pri_stopped(struct pci_dev *pdev)
+{
+	return true;
+}
+
+static inline int pci_pri_status(struct pci_dev *pdev)
+{
+	return -ENODEV;
+}
+#endif /* CONFIG_PCI_PRI */
+
 #endif /* LINUX_PCI_ATS_H*/
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e884096..7fc32af 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -663,6 +663,18 @@
 #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
 #define  PCI_ATS_MIN_STU	12	/* shift of minimum STU block */
 
+/* Page Request Interface */
+#define PCI_PRI_CAP		0x13    /* PRI capability ID */
+#define PCI_PRI_CONTROL_OFF	0x04	/* Offset of control register */
+#define PCI_PRI_STATUS_OFF	0x06	/* Offset of status register */
+#define PCI_PRI_ENABLE		0x0001	/* Enable mask */
+#define PCI_PRI_RESET		0x0002	/* Reset bit mask */
+#define PCI_PRI_STATUS_RF	0x0001  /* Request Failure */
+#define PCI_PRI_STATUS_UPRGI	0x0002  /* Unexpected PRG index */
+#define PCI_PRI_STATUS_STOPPED	0x0100  /* PRI Stopped */
+#define PCI_PRI_MAX_REQ_OFF	0x08	/* Cap offset for max reqs supported */
+#define PCI_PRI_ALLOC_REQ_OFF	0x0c	/* Cap offset for max reqs allowed */
+
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
 #define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */
-- 
1.7.4.1

[PATCH 4/4] PCI: Add support for PASID capability

[Joerg Roedel]

Devices supporting the PASID capability can use multiple
contexts on an IOMMU at the same time. This patch adds
support to manage that capability.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 drivers/pci/Kconfig      |   11 +++++
 drivers/pci/ats.c        |  113 ++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/pci-ats.h  |   31 +++++++++++++
 include/linux/pci_regs.h |    8 +++
 4 files changed, 163 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index fb1e9707..ed7c42e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -94,6 +94,17 @@ config PCI_PRI
 
 	  If unsure, say N.
 
+config PCI_PASID
+	bool "PCI PASID support"
+	depends on PCI
+	select PCI_ATS
+	help
+	  Devices supporting PASIDs can access multiple address spaces
+	  on an IOMMU at the same time. This option compiles code for
+	  that capability into the kernel.
+
+	  If unsure, say N.
+
 config PCI_IOAPIC
 	bool
 	depends on PCI
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index bf892a0..f727a09 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -7,6 +7,7 @@
  * PCI Express I/O Virtualization (IOV) support.
  *   Address Translation Service 1.0
  *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
+ *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
  */
 
 #include <linux/pci-ats.h>
@@ -323,3 +324,115 @@ int pci_pri_status(struct pci_dev *pdev)
 }
 EXPORT_SYMBOL_GPL(pci_pri_status);
 #endif /* CONFIG_PCI_PRI */
+
+#ifdef CONFIG_PCI_PASID
+/**
+ * pci_enable_pasid - Enable the PASID capability
+ * @pdev: PCI device structure
+ * @features: Features to enable
+ *
+ * Returns 0 on success, negative value on error. This function checks
+ * whether the features are actually supported by the device and returns
+ * an error if not.
+ */
+int pci_enable_pasid(struct pci_dev *pdev, int features)
+{
+	u16 control, supported;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control);
+	pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF,     &supported);
+
+	if (!(supported & PCI_PASID_ENABLE))
+		return -EINVAL;
+
+	supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
+
+	/* User wants to enable anything unsupported? */
+	if ((supported & features) != features)
+		return -EINVAL;
+
+	control = PCI_PASID_ENABLE | features;
+
+	pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pci_enable_pasid);
+
+/**
+ * pci_disable_pasid - Disable the PASID capability
+ * @pdev: PCI device structure
+ *
+ */
+void pci_disable_pasid(struct pci_dev *pdev)
+{
+	u16 control = 0;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
+	if (!pos)
+		return;
+
+	pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
+}
+EXPORT_SYMBOL_GPL(pci_disable_pasid);
+
+/**
+ * pci_pasid_features - Check which PASID features are supported
+ * @pdev: PCI device structure
+ *
+ * Returns a negative value when no PASI capability is present.
+ * Otherwise is returns a bitmask with supported features. Current
+ * features reported are:
+ * PCI_PASID_ENABLE - PASID capability can be enabled
+ * PCI_PASID_EXEC - Execute permission supported
+ * PCI_PASID_PRIV - Priviledged mode supported
+ */
+int pci_pasid_features(struct pci_dev *pdev)
+{
+	u16 supported;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
+
+	supported &= PCI_PASID_ENABLE | PCI_PASID_EXEC | PCI_PASID_PRIV;
+
+	return supported;
+}
+EXPORT_SYMBOL_GPL(pci_pasid_features);
+
+#define PASID_NUMBER_SHIFT	8
+#define PASID_NUMBER_MASK	(0x1f << PASID_NUMBER_SHIFT)
+/**
+ * pci_max_pasid - Get maximum number of PASIDs supported by device
+ * @pdev: PCI device structure
+ *
+ * Returns negative value when PASID capability is not present.
+ * Otherwise it returns the numer of supported PASIDs.
+ */
+int pci_max_pasids(struct pci_dev *pdev)
+{
+	u16 supported;
+	int pos;
+
+	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
+	if (!pos)
+		return -EINVAL;
+
+	pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
+
+	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
+
+	return (1 << supported);
+}
+EXPORT_SYMBOL_GPL(pci_max_pasids);
+#endif /* CONFIG_PCI_PASID */
diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index 0713952..e3d0b38 100644
--- a/include/linux/pci-ats.h
+++ b/include/linux/pci-ats.h
@@ -93,4 +93,35 @@ static inline int pci_pri_status(struct pci_dev *pdev)
 }
 #endif /* CONFIG_PCI_PRI */
 
+#ifdef CONFIG_PCI_PASID
+
+extern int pci_enable_pasid(struct pci_dev *pdev, int features);
+extern void pci_disable_pasid(struct pci_dev *pdev);
+extern int pci_pasid_features(struct pci_dev *pdev);
+extern int pci_max_pasids(struct pci_dev *pdev);
+
+#else  /* CONFIG_PCI_PASID */
+
+static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
+{
+	return -EINVAL;
+}
+
+static inline void pci_disable_pasid(struct pci_dev *pdev)
+{
+}
+
+static inline int pci_pasid_features(struct pci_dev *pdev)
+{
+	return -EINVAL;
+}
+
+static inline int pci_max_pasids(struct pci_dev *pdev)
+{
+	return -EINVAL;
+}
+
+#endif /* CONFIG_PCI_PASID */
+
+
 #endif /* LINUX_PCI_ATS_H*/
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 7fc32af..b5d9657 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -675,6 +675,14 @@
 #define PCI_PRI_MAX_REQ_OFF	0x08	/* Cap offset for max reqs supported */
 #define PCI_PRI_ALLOC_REQ_OFF	0x0c	/* Cap offset for max reqs allowed */
 
+/* PASID capability */
+#define PCI_PASID_CAP		0x1b    /* PASID capability ID */
+#define PCI_PASID_CAP_OFF	0x04    /* PASID feature register */
+#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
+#define PCI_PASID_ENABLE	0x01	/* Enable/Supported bit */
+#define PCI_PASID_EXEC		0x02	/* Exec permissions Enable/Supported */
+#define PCI_PASID_PRIV		0x04	/* Priviledge Mode Enable/Support */
+
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
 #define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */
-- 
1.7.4.1

Re: [PATCH 4/4] PCI: Add support for PASID capability

[Bjorn Helgaas]

On Thu, Sep 22, 2011 at 9:49 AM, Joerg Roedel <joerg.roedel@amd.com> wrote:
> Devices supporting the PASID capability can use multiple
> contexts on an IOMMU at the same time. This patch adds
> support to manage that capability.

These all look reasonable to me.

Is there anything else useful you could say in the PASID Kconfig help
text?  I'm guessing it stands for "PCI Address Space ID" or something,
but I have no idea why I might want to enable it.

I didn't coordinate very well with Jesse.  I'm hoping he'll be back
before the 3.2 merge window, but I think we have a few patches queued
up now, and it might be useful to have them in linux-next for a while
before he returns.  I'll look into that.

Bjorn

> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
> ---
>  drivers/pci/Kconfig      |   11 +++++
>  drivers/pci/ats.c        |  113 ++++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/pci-ats.h  |   31 +++++++++++++
>  include/linux/pci_regs.h |    8 +++
>  4 files changed, 163 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index fb1e9707..ed7c42e 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -94,6 +94,17 @@ config PCI_PRI
>
>          If unsure, say N.
>
> +config PCI_PASID
> +       bool "PCI PASID support"
> +       depends on PCI
> +       select PCI_ATS
> +       help
> +         Devices supporting PASIDs can access multiple address spaces
> +         on an IOMMU at the same time. This option compiles code for
> +         that capability into the kernel.
> +
> +         If unsure, say N.
> +
>  config PCI_IOAPIC
>        bool
>        depends on PCI
> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
> index bf892a0..f727a09 100644
> --- a/drivers/pci/ats.c
> +++ b/drivers/pci/ats.c
> @@ -7,6 +7,7 @@
>  * PCI Express I/O Virtualization (IOV) support.
>  *   Address Translation Service 1.0
>  *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
> + *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
>  */
>
>  #include <linux/pci-ats.h>
> @@ -323,3 +324,115 @@ int pci_pri_status(struct pci_dev *pdev)
>  }
>  EXPORT_SYMBOL_GPL(pci_pri_status);
>  #endif /* CONFIG_PCI_PRI */
> +
> +#ifdef CONFIG_PCI_PASID
> +/**
> + * pci_enable_pasid - Enable the PASID capability
> + * @pdev: PCI device structure
> + * @features: Features to enable
> + *
> + * Returns 0 on success, negative value on error. This function checks
> + * whether the features are actually supported by the device and returns
> + * an error if not.
> + */
> +int pci_enable_pasid(struct pci_dev *pdev, int features)
> +{
> +       u16 control, supported;
> +       int pos;
> +
> +       pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
> +       if (!pos)
> +               return -EINVAL;
> +
> +       pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control);
> +       pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF,     &supported);
> +
> +       if (!(supported & PCI_PASID_ENABLE))
> +               return -EINVAL;
> +
> +       supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
> +
> +       /* User wants to enable anything unsupported? */
> +       if ((supported & features) != features)
> +               return -EINVAL;
> +
> +       control = PCI_PASID_ENABLE | features;
> +
> +       pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
> +
> +       return 0;
> +}
> +EXPORT_SYMBOL_GPL(pci_enable_pasid);
> +
> +/**
> + * pci_disable_pasid - Disable the PASID capability
> + * @pdev: PCI device structure
> + *
> + */
> +void pci_disable_pasid(struct pci_dev *pdev)
> +{
> +       u16 control = 0;
> +       int pos;
> +
> +       pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
> +       if (!pos)
> +               return;
> +
> +       pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
> +}
> +EXPORT_SYMBOL_GPL(pci_disable_pasid);
> +
> +/**
> + * pci_pasid_features - Check which PASID features are supported
> + * @pdev: PCI device structure
> + *
> + * Returns a negative value when no PASI capability is present.
> + * Otherwise is returns a bitmask with supported features. Current
> + * features reported are:
> + * PCI_PASID_ENABLE - PASID capability can be enabled
> + * PCI_PASID_EXEC - Execute permission supported
> + * PCI_PASID_PRIV - Priviledged mode supported
> + */
> +int pci_pasid_features(struct pci_dev *pdev)
> +{
> +       u16 supported;
> +       int pos;
> +
> +       pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
> +       if (!pos)
> +               return -EINVAL;
> +
> +       pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
> +
> +       supported &= PCI_PASID_ENABLE | PCI_PASID_EXEC | PCI_PASID_PRIV;
> +
> +       return supported;
> +}
> +EXPORT_SYMBOL_GPL(pci_pasid_features);
> +
> +#define PASID_NUMBER_SHIFT     8
> +#define PASID_NUMBER_MASK      (0x1f << PASID_NUMBER_SHIFT)
> +/**
> + * pci_max_pasid - Get maximum number of PASIDs supported by device
> + * @pdev: PCI device structure
> + *
> + * Returns negative value when PASID capability is not present.
> + * Otherwise it returns the numer of supported PASIDs.
> + */
> +int pci_max_pasids(struct pci_dev *pdev)
> +{
> +       u16 supported;
> +       int pos;
> +
> +       pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
> +       if (!pos)
> +               return -EINVAL;
> +
> +       pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
> +
> +       supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
> +
> +       return (1 << supported);
> +}
> +EXPORT_SYMBOL_GPL(pci_max_pasids);
> +#endif /* CONFIG_PCI_PASID */
> diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
> index 0713952..e3d0b38 100644
> --- a/include/linux/pci-ats.h
> +++ b/include/linux/pci-ats.h
> @@ -93,4 +93,35 @@ static inline int pci_pri_status(struct pci_dev *pdev)
>  }
>  #endif /* CONFIG_PCI_PRI */
>
> +#ifdef CONFIG_PCI_PASID
> +
> +extern int pci_enable_pasid(struct pci_dev *pdev, int features);
> +extern void pci_disable_pasid(struct pci_dev *pdev);
> +extern int pci_pasid_features(struct pci_dev *pdev);
> +extern int pci_max_pasids(struct pci_dev *pdev);
> +
> +#else  /* CONFIG_PCI_PASID */
> +
> +static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
> +{
> +       return -EINVAL;
> +}
> +
> +static inline void pci_disable_pasid(struct pci_dev *pdev)
> +{
> +}
> +
> +static inline int pci_pasid_features(struct pci_dev *pdev)
> +{
> +       return -EINVAL;
> +}
> +
> +static inline int pci_max_pasids(struct pci_dev *pdev)
> +{
> +       return -EINVAL;
> +}
> +
> +#endif /* CONFIG_PCI_PASID */
> +
> +
>  #endif /* LINUX_PCI_ATS_H*/
> diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
> index 7fc32af..b5d9657 100644
> --- a/include/linux/pci_regs.h
> +++ b/include/linux/pci_regs.h
> @@ -675,6 +675,14 @@
>  #define PCI_PRI_MAX_REQ_OFF    0x08    /* Cap offset for max reqs supported */
>  #define PCI_PRI_ALLOC_REQ_OFF  0x0c    /* Cap offset for max reqs allowed */
>
> +/* PASID capability */
> +#define PCI_PASID_CAP          0x1b    /* PASID capability ID */
> +#define PCI_PASID_CAP_OFF      0x04    /* PASID feature register */
> +#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
> +#define PCI_PASID_ENABLE       0x01    /* Enable/Supported bit */
> +#define PCI_PASID_EXEC         0x02    /* Exec permissions Enable/Supported */
> +#define PCI_PASID_PRIV         0x04    /* Priviledge Mode Enable/Support */
> +
>  /* Single Root I/O Virtualization */
>  #define PCI_SRIOV_CAP          0x04    /* SR-IOV Capabilities */
>  #define  PCI_SRIOV_CAP_VFM     0x01    /* VF Migration Capable */
> --
> 1.7.4.1
>
>
> --
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> Please read the FAQ at  http://www.tux.org/lkml/
>

Re: [PATCH 4/4] PCI: Add support for PASID capability

[Joerg Roedel]

On Mon, Sep 26, 2011 at 02:58:58PM -0600, Bjorn Helgaas wrote:
> On Thu, Sep 22, 2011 at 9:49 AM, Joerg Roedel <joerg.roedel@amd.com> wrote:
> > Devices supporting the PASID capability can use multiple
> > contexts on an IOMMU at the same time. This patch adds
> > support to manage that capability.
> 
> These all look reasonable to me.
> 
> Is there anything else useful you could say in the PASID Kconfig help
> text?  I'm guessing it stands for "PCI Address Space ID" or something,
> but I have no idea why I might want to enable it.

PASID stands for Process Address Space ID, it basically allows a PCI
device to access multiple IO address spaces at the same time using an
IOMMU. Users should enable it when they want to compile an IOMMU driver
into the kernel that supports PASIDs for the translated devices.
I'll add all that information to the Kconfig help. Thanks a lot for your
feedback :)

> I didn't coordinate very well with Jesse.  I'm hoping he'll be back
> before the 3.2 merge window, but I think we have a few patches queued
> up now, and it might be useful to have them in linux-next for a while
> before he returns.  I'll look into that.

Great, thanks again.

Regards,

	Joerg

Re: [PATCH 4/4] PCI: Add support for PASID capability

[Valdis.Kletnieks]

[-- Attachment #1: Type: text/plain, Size: 578 bytes --]

On Tue, 27 Sep 2011 00:15:39 +0200, Joerg Roedel said:

> PASID stands for Process Address Space ID, it basically allows a PCI
> device to access multiple IO address spaces at the same time using an
> IOMMU. Users should enable it when they want to compile an IOMMU driver
> into the kernel that supports PASIDs for the translated devices.
> I'll add all that information to the Kconfig help. Thanks a lot for your
> feedback :)

Is this a case where the PCI device drivers in question should be doing a
'select' or 'depends on' if they support talking to an IOMMU using PASID?

[-- Attachment #2: Type: application/pgp-signature, Size: 227 bytes --]

Re: [PATCH 4/4] PCI: Add support for PASID capability

[Roedel, Joerg]

On Wed, Sep 28, 2011 at 03:18:15PM -0400, Valdis.Kletnieks@vt.edu wrote:
> On Tue, 27 Sep 2011 00:15:39 +0200, Joerg Roedel said:
> 
> > PASID stands for Process Address Space ID, it basically allows a PCI
> > device to access multiple IO address spaces at the same time using an
> > IOMMU. Users should enable it when they want to compile an IOMMU driver
> > into the kernel that supports PASIDs for the translated devices.
> > I'll add all that information to the Kconfig help. Thanks a lot for your
> > feedback :)
> 
> Is this a case where the PCI device drivers in question should be doing a
> 'select' or 'depends on' if they support talking to an IOMMU using PASID?

Exactly. In fact, I plan to put the functionality which handles these
capabilities and the fault-handling in a seperate module where all
device drivers can use it in an easy way.

	Joerg

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo, Andrew Bowd
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632

Re: [PATCH 0/4] Support for PRI and PASID capability

[Joerg Roedel]

Hi Jesse,

On Thu, Sep 22, 2011 at 05:49:07PM +0200, Joerg Roedel wrote:
> here is a patch-set that enables support for the PRI and PASID
> capabilities in the Linux PCI core. These capabilities of a PCIe device
> are tightly coupled with ATS, but not with IOV. So these patches start
> by moving the ATS code into its own file: ats.c.
> 
> Support for the other two capabilities is based on that change. Please
> review the patches and let me know of any objections you might have.

Have you had a chance to look at these patches? Please let me know any
questions or objections you might have.

Thanks,

	Joerg

Re: [PATCH 0/4] Support for PRI and PASID capability

[Bjorn Helgaas]

On Mon, Sep 26, 2011 at 8:26 AM, Joerg Roedel <joro@8bytes.org> wrote:
>
> Hi Jesse,
>
> On Thu, Sep 22, 2011 at 05:49:07PM +0200, Joerg Roedel wrote:
> > here is a patch-set that enables support for the PRI and PASID
> > capabilities in the Linux PCI core. These capabilities of a PCIe device
> > are tightly coupled with ATS, but not with IOV. So these patches start
> > by moving the ATS code into its own file: ats.c.
> >
> > Support for the other two capabilities is based on that change. Please
> > review the patches and let me know of any objections you might have.
>
> Have you had a chance to look at these patches? Please let me know any
> questions or objections you might have.

Jesse's on vacation, but I'll take a look and give you my opinion
(which won't necessarily coincide with Jesse's, but I guess it's a
start :)).

Bjorn

Re: [PATCH 0/4] Support for PRI and PASID capability

[Joerg Roedel]

On Mon, Sep 26, 2011 at 02:42:01PM -0600, Bjorn Helgaas wrote:
> On Mon, Sep 26, 2011 at 8:26 AM, Joerg Roedel <joro@8bytes.org> wrote:
> >
> > Hi Jesse,
> >
> > On Thu, Sep 22, 2011 at 05:49:07PM +0200, Joerg Roedel wrote:
> > > here is a patch-set that enables support for the PRI and PASID
> > > capabilities in the Linux PCI core. These capabilities of a PCIe device
> > > are tightly coupled with ATS, but not with IOV. So these patches start
> > > by moving the ATS code into its own file: ats.c.
> > >
> > > Support for the other two capabilities is based on that change. Please
> > > review the patches and let me know of any objections you might have.
> >
> > Have you had a chance to look at these patches? Please let me know any
> > questions or objections you might have.
> 
> Jesse's on vacation, but I'll take a look and give you my opinion
> (which won't necessarily coincide with Jesse's, but I guess it's a
> start :)).

Great. Thanks a lot :)

	Joerg