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* [RFC] mark Netlogic XLR chip as SMT capable
@ 2011-10-02  7:26 Hillf Danton
  2011-10-02  8:30   ` Jayachandran C.
  0 siblings, 1 reply; 8+ messages in thread
From: Hillf Danton @ 2011-10-02  7:26 UTC (permalink / raw)
  To: linux-mips; +Cc: Jayachandran C., Ralf Baechle

Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.

If XLR chip is marked to be SMT capable, linux scheduler then could do more,
say idle load balancing.

Any comment is welcom, thanks.

Signed-off-by: Hillf Danton <dhillf@gmail.com>
---

--- a/arch/mips/netlogic/xlr/smp.c	Sun Oct  2 14:15:28 2011
+++ b/arch/mips/netlogic/xlr/smp.c	Sun Oct  2 14:15:58 2011
@@ -176,6 +176,7 @@ void __init nlm_smp_setup(void)

 void nlm_prepare_cpus(unsigned int max_cpus)
 {
+	smp_num_siblings = 4;
 }

 struct plat_smp_ops nlm_smp_ops = {
--- a/arch/mips/kernel/smp.c	Sun Oct  2 14:12:09 2011
+++ b/arch/mips/kernel/smp.c	Sun Oct  2 14:14:58 2011
@@ -73,7 +73,12 @@ static inline void set_cpu_sibling_map(i

 	if (smp_num_siblings > 1) {
 		for_each_cpu_mask(i, cpu_sibling_setup_map) {
-			if (cpu_data[cpu].core == cpu_data[i].core) {
+			if (current_cpu_type() == CPU_XLR) {
+				if (((i>>2) & 0x7) == ((cpu>>2) & 0x7))
+					goto set;
+			}
+			else if (cpu_data[cpu].core == cpu_data[i].core) {
+set:
 				cpu_set(i, cpu_sibling_map[cpu]);
 				cpu_set(cpu, cpu_sibling_map[i]);
 			}

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2011-10-04 10:48 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-10-02  7:26 [RFC] mark Netlogic XLR chip as SMT capable Hillf Danton
2011-10-02  8:30 ` Jayachandran C.
2011-10-02  8:30   ` Jayachandran C.
2011-10-03  5:46   ` Hillf Danton
2011-10-03 10:32     ` Ralf Baechle
2011-10-03 10:39       ` Jayachandran C.
2011-10-03 10:39         ` Jayachandran C.
2011-10-04 10:48         ` Hillf Danton

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