From: 陳韋任 <chenwj@iis.sinica.edu.tw>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Blue Swirl" <blauwirbel@gmail.com>,
"Andreas Färber" <andreas.faerber@web.de>,
Lluís <xscript@gmx.net>, "Greg McGary" <greg.mcgary@gmail.com>,
"qemu-devel Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] Multi heterogenous CPU archs for SoC sim?
Date: Fri, 21 Oct 2011 15:26:17 +0800 [thread overview]
Message-ID: <20111021072617.GA2130@cs.nctu.edu.tw> (raw)
In-Reply-To: <CAFEAcA85UyU1x-H_f7JFxs6Hw8hdDyWPAd77JP1DHX3fDqiFVg@mail.gmail.com>
> We may want the tb cache to be per-core anyway (and one thread per core),
> which would avoid the problem of trying to wedge everything into one set
> of tb_flags.
>
> (Has anybody had a look at http://sourceforge.net/p/coremu/home/Home/ ?)
COREMU treats QEMU as an entity and lauches multiple QEMUs at the same
time. QEMUs communicates to each other by using a underlying thin layer
provided by COREMU. I think this approach is much clean than trying to
parallelize QEMU itself.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
next prev parent reply other threads:[~2011-10-21 7:26 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-25 18:44 [Qemu-devel] Multi heterogenous CPU archs for SoC sim? Greg McGary
2011-05-25 19:20 ` Peter Maydell
2011-05-26 19:11 ` Blue Swirl
2011-05-26 20:07 ` Lluís
2011-05-26 20:31 ` Blue Swirl
2011-05-27 14:23 ` Lluís
2011-10-20 22:51 ` Andreas Färber
2011-10-21 6:58 ` Peter Maydell
2011-10-21 7:26 ` 陳韋任 [this message]
2011-10-21 20:36 ` Andreas
2011-10-22 8:12 ` 陳韋任
2011-10-21 15:41 ` Lluís Vilanova
2011-10-21 22:05 ` Andreas Färber
2011-10-22 9:32 ` Peter Maydell
2011-05-26 20:10 ` Andreas Färber
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