From: Ralf Baechle <ralf@linux-mips.org>
To: ddaney.cavm@gmail.com
Cc: linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>
Subject: Re: [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips.
Date: Wed, 16 Nov 2011 00:59:54 +0000 [thread overview]
Message-ID: <20111116005954.GO25384@linux-mips.org> (raw)
In-Reply-To: <1321400775-32353-2-git-send-email-ddaney.cavm@gmail.com>
Queued for 3.3. Thanks,
Ralf
next prev parent reply other threads:[~2011-11-16 1:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
2011-11-15 23:46 ` [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips ddaney.cavm
2011-11-16 0:59 ` Ralf Baechle [this message]
2011-11-15 23:46 ` [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
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