* [PATCH RESEND 02/17] MIPS: lantiq: change ltq_request_gpio() call signature
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:19 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 03/17] MIPS: lantiq: make irq.c support the FALC-ON John Crispin
` (15 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins.
This was XWAY specific. In order to also accomodate SoCs that require more bits
we use a 32bit mask instead. This way the call signature is consistent between
XWAY and FALC-ON.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +-
arch/mips/lantiq/xway/gpio.c | 8 ++--
arch/mips/lantiq/xway/gpio_stp.c | 6 +-
arch/mips/pci/pci-lantiq.c | 40 +++++++++----------
4 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 9ea7043..a6521ec 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -151,8 +151,8 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) {
}
/* request a non-gpio and set the PIO config */
-extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
- unsigned int alt1, unsigned int dir, const char *name);
+extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name);
extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
extern void ltq_cgu_enable(unsigned int clk);
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index d2fa98f..f204f6c 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio)
}
EXPORT_SYMBOL(irq_to_gpio);
-int ltq_gpio_request(unsigned int pin, unsigned int alt0,
- unsigned int alt1, unsigned int dir, const char *name)
+int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name)
{
int id = 0;
@@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
pin -= PINS_PER_PORT;
id++;
}
- if (alt0)
+ if (mux & 0x2)
ltq_gpio_setbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
else
ltq_gpio_clearbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL0, pin);
- if (alt1)
+ if (mux & 0x1)
ltq_gpio_setbit(ltq_gpio_port[id].membase,
LTQ_GPIO_ALTSEL1, pin);
else
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index ff9991c..2c78660 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = {
static int ltq_stp_hw_init(void)
{
/* the 3 pins used to control the external stp */
- ltq_gpio_request(4, 1, 0, 1, "stp-st");
- ltq_gpio_request(5, 1, 0, 1, "stp-d");
- ltq_gpio_request(6, 1, 0, 1, "stp-sh");
+ ltq_gpio_request(4, 2, 1, "stp-st");
+ ltq_gpio_request(5, 2, 1, "stp-d");
+ ltq_gpio_request(6, 2, 1, "stp-sh");
/* sane defaults */
ltq_stp_w32(0, LTQ_STP_AR);
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index be1e1af..3bf42c8 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -69,29 +69,28 @@
#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
struct ltq_pci_gpio_map {
- int pin;
- int alt0;
- int alt1;
- int dir;
+ unsigned int pin;
+ unsigned int mux;
+ unsigned char dir;
char *name;
};
/* the pci core can make use of the following gpios */
static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
- { 0, 1, 0, 0, "pci-exin0" },
- { 1, 1, 0, 0, "pci-exin1" },
- { 2, 1, 0, 0, "pci-exin2" },
- { 39, 1, 0, 0, "pci-exin3" },
- { 10, 1, 0, 0, "pci-exin4" },
- { 9, 1, 0, 0, "pci-exin5" },
- { 30, 1, 0, 1, "pci-gnt1" },
- { 23, 1, 0, 1, "pci-gnt2" },
- { 19, 1, 0, 1, "pci-gnt3" },
- { 38, 1, 0, 1, "pci-gnt4" },
- { 29, 1, 0, 0, "pci-req1" },
- { 31, 1, 0, 0, "pci-req2" },
- { 3, 1, 0, 0, "pci-req3" },
- { 37, 1, 0, 0, "pci-req4" },
+ { .pin = 0, .mux = 2, .dir = 0, .name = "pci-exin0" },
+ { .pin = 1, .mux = 2, .dir = 0, .name = "pci-exin1" },
+ { .pin = 2, .mux = 2, .dir = 0, .name = "pci-exin2" },
+ { .pin = 39, .mux = 2, .dir = 0, .name = "pci-exin3" },
+ { .pin = 10, .mux = 2, .dir = 0, .name = "pci-exin4" },
+ { .pin = 9, .mux = 2, .dir = 0, .name = "pci-exin5" },
+ { .pin = 30, .mux = 2, .dir = 1, .name = "pci-gnt1" },
+ { .pin = 23, .mux = 2, .dir = 1, .name = "pci-gnt2" },
+ { .pin = 19, .mux = 2, .dir = 1, .name = "pci-gnt3" },
+ { .pin = 38, .mux = 2, .dir = 1, .name = "pci-gnt4" },
+ { .pin = 29, .mux = 2, .dir = 0, .name = "pci-req1" },
+ { .pin = 31, .mux = 2, .dir = 0, .name = "pci-req2" },
+ { .pin = 3, .mux = 2, .dir = 0, .name = "pci-req3" },
+ { .pin = 37, .mux = 2, .dir = 0, .name = "pci-req4" },
};
__iomem void *ltq_pci_mapped_cfg;
@@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio)
for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
if (gpio & (1 << i)) {
ltq_gpio_request(ltq_pci_gpio_map[i].pin,
- ltq_pci_gpio_map[i].alt0,
- ltq_pci_gpio_map[i].alt1,
+ ltq_pci_gpio_map[i].mux,
ltq_pci_gpio_map[i].dir,
ltq_pci_gpio_map[i].name);
}
}
- ltq_gpio_request(21, 0, 0, 1, "pci-reset");
+ ltq_gpio_request(21, 0, 1, "pci-reset");
ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
}
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 03/17] MIPS: lantiq: make irq.c support the FALC-ON
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
2012-01-11 20:44 ` [PATCH RESEND 02/17] MIPS: lantiq: change ltq_request_gpio() call signature John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:19 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 04/17] MIPS: lantiq: add basic support for FALC-ON John Crispin
` (14 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
There are minor differences in how irqs work on xway and falcon socs.
Xway needs 2 quirks that we need to disable for falcon to also work with
this code.
* EBU irq does not need to send a special ack to the EBU
* The EIU does not exist
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/irq.c | 24 +++++++++++++-----------
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index d673731..3b8cea5 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int module)
do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
/* if this is a EBU irq, we need to ack it or get a deadlock */
- if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
+ if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
LTQ_EBU_PCC_ISTAT);
}
@@ -259,17 +259,19 @@ void __init arch_init_irq(void)
if (!ltq_icu_membase)
panic("Failed to remap icu memory");
- if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
- panic("Failed to insert eiu memory");
+ if (LTQ_EIU_BASE_ADDR) {
+ if (insert_resource(&iomem_resource, <q_eiu_resource) < 0)
+ panic("Failed to insert eiu memory");
- if (request_mem_region(ltq_eiu_resource.start,
- resource_size(<q_eiu_resource), "eiu") < 0)
- panic("Failed to request eiu memory");
+ if (request_mem_region(ltq_eiu_resource.start,
+ resource_size(<q_eiu_resource), "eiu") < 0)
+ panic("Failed to request eiu memory");
- ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
+ ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
resource_size(<q_eiu_resource));
- if (!ltq_eiu_membase)
- panic("Failed to remap eiu memory");
+ if (!ltq_eiu_membase)
+ panic("Failed to remap eiu memory");
+ }
/* make sure all irqs are turned off by default */
for (i = 0; i < 5; i++)
@@ -295,8 +297,8 @@ void __init arch_init_irq(void)
for (i = INT_NUM_IRQ0;
i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
- if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
- (i == LTQ_EIU_IR2))
+ if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
+ (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR)
irq_set_chip_and_handler(i, <q_eiu_type,
handle_level_irq);
/* EIU3-5 only exist on ar9 and vr9 */
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 04/17] MIPS: lantiq: add basic support for FALC-ON
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
2012-01-11 20:44 ` [PATCH RESEND 02/17] MIPS: lantiq: change ltq_request_gpio() call signature John Crispin
2012-01-11 20:44 ` [PATCH RESEND 03/17] MIPS: lantiq: make irq.c support the FALC-ON John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-11 20:44 ` [PATCH RESEND 05/17] MIPS: lantiq: add support for FALC-ON GPIOs John Crispin
` (13 subsequent siblings)
16 siblings, 0 replies; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++
arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++
.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 152 +++++++++++
arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
arch/mips/lantiq/Kconfig | 4 +
arch/mips/lantiq/Makefile | 1 +
arch/mips/lantiq/Platform | 1 +
arch/mips/lantiq/falcon/Makefile | 1 +
arch/mips/lantiq/falcon/clk.c | 44 ++++
arch/mips/lantiq/falcon/devices.c | 87 +++++++
arch/mips/lantiq/falcon/devices.h | 18 ++
arch/mips/lantiq/falcon/prom.c | 93 +++++++
arch/mips/lantiq/falcon/reset.c | 91 +++++++
arch/mips/lantiq/falcon/sysctrl.c | 183 +++++++++++++
14 files changed, 962 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
create mode 100644 arch/mips/lantiq/falcon/Makefile
create mode 100644 arch/mips/lantiq/falcon/clk.c
create mode 100644 arch/mips/lantiq/falcon/devices.c
create mode 100644 arch/mips/lantiq/falcon/devices.h
create mode 100644 arch/mips/lantiq/falcon/prom.c
create mode 100644 arch/mips/lantiq/falcon/reset.c
create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
new file mode 100644
index 0000000..4dc6466
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -0,0 +1,268 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
+ */
+
+#ifndef _FALCON_IRQ__
+#define _FALCON_IRQ__
+
+#define INT_NUM_IRQ0 8
+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
+#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
+#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
+#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
+#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
+#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define MIPS_CPU_TIMER_IRQ 7
+
+/* HOST IF Event Interrupt */
+#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0)
+/* HOST IF Mailbox0 Receive Interrupt */
+#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1)
+/* HOST IF Mailbox0 Transmit Interrupt */
+#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2)
+/* HOST IF Mailbox1 Receive Interrupt */
+#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3)
+/* HOST IF Mailbox1 Transmit Interrupt */
+#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4)
+/* I2C Last Single Data Transfer Request */
+#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8)
+/* I2C Single Data Transfer Request */
+#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9)
+/* I2C Last Burst Data Transfer Request */
+#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10)
+/* I2C Burst Data Transfer Request */
+#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11)
+/* I2C Error Interrupt */
+#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12)
+/* I2C Protocol Interrupt */
+#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13)
+/* SSC Transmit Interrupt */
+#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14)
+/* SSC Receive Interrupt */
+#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15)
+/* SSC Error Interrupt */
+#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16)
+/* SSC Frame Interrupt */
+#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17)
+/* Advanced Encryption Standard Interrupt */
+#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27)
+/* Secure Hash Algorithm Interrupt */
+#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28)
+/* PCM Receive Interrupt */
+#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29)
+/* PCM Transmit Interrupt */
+#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30)
+/* PCM Transmit Crash Interrupt */
+#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31)
+
+/* EBU Serial Flash Command Error */
+#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0)
+/* EBU Serial Flash Command Overwrite Error */
+#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1)
+/* EBU Serial Flash Busy */
+#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2)
+/* External Interrupt from GPIO P0 */
+#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4)
+/* External Interrupt from GPIO P1 */
+#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5)
+/* External Interrupt from GPIO P2 */
+#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6)
+/* External Interrupt from GPIO P3 */
+#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7)
+/* External Interrupt from GPIO P4 */
+#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8)
+/* 8kHz backup interrupt derived from core-PLL */
+#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10)
+/* FSC Timer Interrupt 0 */
+#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11)
+/* FSC Timer Interrupt 1 */
+#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12)
+/* 8kHz root interrupt derived from GPON interface */
+#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13)
+/* Time of Day */
+#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14)
+/* PMA Interrupt from IntNode of the 200MHz Domain */
+#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15)
+/* PMA Interrupt from IntNode of the TX Clk Domain */
+#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16)
+/* PMA Interrupt from IntNode of the RX Clk Domain */
+#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17)
+/* SYS1 Interrupt */
+#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20)
+/* SYS GPE Interrupt */
+#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21)
+/* Watchdog Access Error Interrupt */
+#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24)
+/* Watchdog Prewarning Interrupt */
+#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25)
+/* SBIU interrupt */
+#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27)
+/* FPI Bus Control Unit Interrupt */
+#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29)
+/* DDR Controller Interrupt */
+#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30)
+/* Crossbar Error Interrupt */
+#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31)
+
+/* ICTRLL 0 Interrupt */
+#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0)
+/* ICTRLL 1 Interrupt */
+#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1)
+/* ICTRLL 2 Interrupt */
+#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2)
+/* ICTRLL 3 Interrupt */
+#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3)
+/* OCTRLL 0 Interrupt */
+#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4)
+/* OCTRLL 1 Interrupt */
+#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5)
+/* OCTRLL 2 Interrupt */
+#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6)
+/* OCTRLL 3 Interrupt */
+#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7)
+/* OCTRLG Interrupt */
+#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9)
+/* IQM Interrupt */
+#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10)
+/* FSQM Interrupt */
+#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11)
+/* TMU Interrupt */
+#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12)
+/* LINK1 Interrupt */
+#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14)
+/* ICTRLC 0 Interrupt */
+#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16)
+/* ICTRLC 1 Interrupt */
+#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17)
+/* OCTRLC Interrupt */
+#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18)
+/* CONFIG Break Interrupt */
+#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19)
+/* CONFIG Interrupt */
+#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20)
+/* Dispatcher Interrupt */
+#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21)
+/* TBM Interrupt */
+#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22)
+/* GTC Downstream Interrupt */
+#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29)
+/* GTC Upstream Interrupt */
+#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30)
+/* EIM Interrupt */
+#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31)
+
+/* ASC0 Transmit Interrupt */
+#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0)
+/* ASC0 Receive Interrupt */
+#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1)
+/* ASC0 Error Interrupt */
+#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2)
+/* ASC0 Transmit Buffer Interrupt */
+#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3)
+/* ASC0 Autobaud Start Interrupt */
+#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4)
+/* ASC0 Autobaud Detection Interrupt */
+#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5)
+/* ASC1 Modem Status Interrupt */
+#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6)
+/* ASC0 Soft Flow Control Interrupt */
+#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7)
+/* ASC1 Transmit Interrupt */
+#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8)
+/* ASC1 Receive Interrupt */
+#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9)
+/* ASC1 Error Interrupt */
+#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10)
+/* ASC1 Transmit Buffer Interrupt */
+#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11)
+/* ASC1 Autobaud Start Interrupt */
+#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12)
+/* ASC1 Autobaud Detection Interrupt */
+#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13)
+/* ASC1 Modem Status Interrupt */
+#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14)
+/* ASC1 Soft Flow Control Interrupt */
+#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15)
+/* GPTC Timer/Counter 1A Interrupt */
+#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16)
+/* GPTC Timer/Counter 1B Interrupt */
+#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17)
+/* GPTC Timer/Counter 2A Interrupt */
+#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18)
+/* GPTC Timer/Counter 2B Interrupt */
+#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19)
+/* GPTC Timer/Counter 3A Interrupt */
+#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20)
+/* GPTC Timer/Counter 3B Interrupt */
+#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21)
+/* DFEV0, Channel 1 Transmit Interrupt */
+#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26)
+/* DFEV0, Channel 1 Receive Interrupt */
+#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27)
+/* DFEV0, Channel 1 General Purpose Interrupt */
+#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28)
+/* DFEV0, Channel 0 Transmit Interrupt */
+#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29)
+/* DFEV0, Channel 0 Receive Interrupt */
+#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30)
+/* DFEV0, Channel 0 General Purpose Interrupt */
+#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31)
+
+/* ICTRLL 0 Error */
+#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0)
+/* ICTRLL 1 Error */
+#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1)
+/* ICTRLL 2 Error */
+#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2)
+/* ICTRLL 3 Error */
+#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3)
+/* OCTRLL 0 Error */
+#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4)
+/* OCTRLL 1 Error */
+#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5)
+/* OCTRLL 2 Error */
+#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6)
+/* OCTRLL 3 Error */
+#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7)
+/* ICTRLG Error */
+#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8)
+/* OCTRLG Error */
+#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9)
+/* IQM Error */
+#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10)
+/* FSQM Error */
+#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11)
+/* TMU Error */
+#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12)
+/* MPS Status Interrupt #0 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14)
+/* MPS Status Interrupt #1 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15)
+/* MPS Status Interrupt #2 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16)
+/* MPS Status Interrupt #3 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17)
+/* MPS Status Interrupt #4 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18)
+/* MPS Status Interrupt #5 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19)
+/* MPS Status Interrupt #6 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20)
+/* MPS Status Interrupt #7 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21)
+/* MPS Status Interrupt #8 (VPE1 to VPE0) */
+#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22)
+/* VPE0 Exception Level Flag Interrupt */
+#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29)
+/* VPE0 Error Level Flag Interrupt */
+#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30)
+/* VPE0 Performance Monitoring Counter Interrupt */
+#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31)
+
+#endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
new file mode 100644
index 0000000..2caccd9
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
@@ -0,0 +1,18 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ */
+
+#ifndef __FALCON_IRQ_H
+#define __FALCON_IRQ_H
+
+#include <falcon_irq.h>
+
+#define NR_IRQS 328
+
+#include_next <irq.h>
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
new file mode 100644
index 0000000..22f8774
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -0,0 +1,152 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LTQ_FALCON_H__
+#define _LTQ_FALCON_H__
+
+#ifdef CONFIG_SOC_FALCON
+
+#include <lantiq.h>
+
+/* Chip IDs */
+#define SOC_ID_FALCON 0x01B8
+
+/* SoC Types */
+#define SOC_TYPE_FALCON 0x01
+
+/* ASC0/1 - serial port */
+#define LTQ_ASC0_BASE_ADDR 0x1E100C00
+#define LTQ_ASC1_BASE_ADDR 0x1E100B00
+#define LTQ_ASC_SIZE 0x100
+
+#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
+#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
+#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
+
+/*
+ * during early_printk no ioremap possible at this early stage
+ * lets use KSEG1 instead
+ */
+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
+
+/* ICU - interrupt control unit */
+#define LTQ_ICU_BASE_ADDR 0x1F880200
+#define LTQ_ICU_SIZE 0x100
+
+/* WDT */
+#define LTQ_WDT_BASE_ADDR 0x1F8803F0
+#define LTQ_WDT_SIZE 0x10
+
+#define LTQ_RST_CAUSE_WDTRST 0x0002
+
+/* EBU - external bus unit */
+#define LTQ_EBU_BASE_ADDR 0x18000000
+#define LTQ_EBU_SIZE 0x0100
+
+#define LTQ_EBU_MODCON 0x000C
+
+/* GPIO */
+#define LTQ_GPIO0_BASE_ADDR 0x1D810000
+#define LTQ_GPIO0_SIZE 0x0080
+#define LTQ_GPIO1_BASE_ADDR 0x1E800100
+#define LTQ_GPIO1_SIZE 0x0080
+#define LTQ_GPIO2_BASE_ADDR 0x1D810100
+#define LTQ_GPIO2_SIZE 0x0080
+#define LTQ_GPIO3_BASE_ADDR 0x1E800200
+#define LTQ_GPIO3_SIZE 0x0080
+#define LTQ_GPIO4_BASE_ADDR 0x1E800300
+#define LTQ_GPIO4_SIZE 0x0080
+#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000
+#define LTQ_PADCTRL0_SIZE 0x0100
+#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400
+#define LTQ_PADCTRL1_SIZE 0x0100
+#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000
+#define LTQ_PADCTRL2_SIZE 0x0100
+#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500
+#define LTQ_PADCTRL3_SIZE 0x0100
+#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
+#define LTQ_PADCTRL4_SIZE 0x0100
+
+/* CHIP ID */
+#define LTQ_STATUS_BASE_ADDR 0x1E802000
+
+#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
+#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
+#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
+
+/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
+#define LTQ_SYS1_BASE_ADDR 0x1EF00000
+#define LTQ_SYS1_SIZE 0x0100
+#define LTQ_STATUS_BASE_ADDR 0x1E802000
+#define LTQ_STATUS_SIZE 0x0080
+#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000
+#define LTQ_SYS_ETH_SIZE 0x0100
+#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000
+#define LTQ_SYS_GPE_SIZE 0x0100
+
+#define SYSCTL_SYS1 0
+#define SYSCTL_SYSETH 1
+#define SYSCTL_SYSGPE 2
+
+/* Activation Status Register */
+#define ACTS_ASC1_ACT 0x00000800
+#define ACTS_P0 0x00010000
+#define ACTS_P1 0x00010000
+#define ACTS_P2 0x00020000
+#define ACTS_P3 0x00020000
+#define ACTS_P4 0x00040000
+#define ACTS_PADCTRL0 0x00100000
+#define ACTS_PADCTRL1 0x00100000
+#define ACTS_PADCTRL2 0x00200000
+#define ACTS_PADCTRL3 0x00200000
+#define ACTS_PADCTRL4 0x00400000
+
+extern void ltq_sysctl_activate(int module, unsigned int mask);
+extern void ltq_sysctl_deactivate(int module, unsigned int mask);
+extern void ltq_sysctl_clken(int module, unsigned int mask);
+extern void ltq_sysctl_clkdis(int module, unsigned int mask);
+extern void ltq_sysctl_reboot(int module, unsigned int mask);
+extern int ltq_gpe_is_activated(unsigned int mask);
+
+/* global register ranges */
+extern void __iomem *ltq_ebu_membase;
+extern void __iomem *ltq_sys1_membase;
+static inline void ltq_ebu_w32(u32 v, u32 r) {
+ ltq_w32(v, ltq_ebu_membase + r);
+};
+static inline u32 ltq_ebu_r32(u32 r) {
+ return ltq_r32(ltq_ebu_membase + r);
+};
+static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) {
+ ltq_ebu_w32((ltq_ebu_r32(r) & ~c) | s, r);
+}
+static inline void ltq_sys1_w32(u32 v, u32 r) {
+ ltq_w32(v, ltq_sys1_membase + r);
+};
+static inline u32 ltq_sys1_r32(u32 r) {
+ return ltq_r32(ltq_sys1_membase + r);
+};
+static inline void ltq_sys1_w32_mask(u32 c, u32 s, u32 r) {
+ ltq_sys1_w32((ltq_sys1_r32(r) & ~c) | s, r);
+}
+
+/* gpio_request wrapper to help configure the pin */
+extern int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name);
+extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
+
+/* to keep the irq code generic we need to define these to 0 as falcon
+ has no EIU/EBU */
+#define LTQ_EIU_BASE_ADDR 0
+#define LTQ_EBU_PCC_ISTAT 0
+
+#define ltq_is_ar9() 0
+#define ltq_is_vr9() 0
+
+#endif /* CONFIG_SOC_FALCON */
+#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index daaa3f7..1a09f29 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -26,6 +26,7 @@ extern unsigned int ltq_get_soc_type(void);
/* clock speeds */
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
+#define CLOCK_100M 100000000
#define CLOCK_111M 111111111
#define CLOCK_133M 133333333
#define CLOCK_167M 166666667
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 3fccf21..cb6b39f 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -16,8 +16,12 @@ config SOC_XWAY
bool "XWAY"
select SOC_TYPE_XWAY
select HW_HAS_PCI
+
+config SOC_FALCON
+ bool "FALCON"
endchoice
source "arch/mips/lantiq/xway/Kconfig"
+source "arch/mips/lantiq/falcon/Kconfig"
endif
diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
index e5dae0e..7e9c69e 100644
--- a/arch/mips/lantiq/Makefile
+++ b/arch/mips/lantiq/Makefile
@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
+obj-$(CONFIG_SOC_FALCON) += falcon/
diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
index f3dff05..b3ec498 100644
--- a/arch/mips/lantiq/Platform
+++ b/arch/mips/lantiq/Platform
@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/
cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
load-$(CONFIG_LANTIQ) = 0xffffffff80002000
cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
+cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
new file mode 100644
index 0000000..e9c7455
--- /dev/null
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -0,0 +1 @@
+obj-y := clk.o prom.o reset.o sysctrl.o devices.o
diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
new file mode 100644
index 0000000..afe1b52
--- /dev/null
+++ b/arch/mips/lantiq/falcon/clk.c
@@ -0,0 +1,44 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/ioport.h>
+#include <linux/export.h>
+
+#include <lantiq_soc.h>
+
+#include "devices.h"
+
+/* CPU0 Clock Control Register */
+#define LTQ_SYS1_CPU0CC 0x0040
+/* clock divider bit */
+#define LTQ_CPU0CC_CPUDIV 0x0001
+
+unsigned int
+ltq_get_io_region_clock(void)
+{
+ return CLOCK_200M;
+}
+EXPORT_SYMBOL(ltq_get_io_region_clock);
+
+unsigned int
+ltq_get_cpu_hz(void)
+{
+ if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
+ return CLOCK_200M;
+ else
+ return CLOCK_400M;
+}
+EXPORT_SYMBOL(ltq_get_cpu_hz);
+
+unsigned int
+ltq_get_fpi_hz(void)
+{
+ return CLOCK_100M;
+}
+EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
new file mode 100644
index 0000000..c4606f2
--- /dev/null
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -0,0 +1,87 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/nand.h>
+
+#include <lantiq_soc.h>
+
+#include "devices.h"
+
+/* nand flash */
+/* address lines used for NAND control signals */
+#define NAND_ADDR_ALE 0x10000
+#define NAND_ADDR_CLE 0x20000
+/* Ready/Busy Status */
+#define MODCON_STS 0x0002
+/* Ready/Busy Status Edge */
+#define MODCON_STSEDGE 0x0004
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+static int
+falcon_nand_ready(struct mtd_info *mtd)
+{
+ u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
+
+ return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
+ (MODCON_STS | MODCON_STSEDGE)));
+}
+
+static void
+falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
+
+ if (ctrl & NAND_CLE)
+ nandaddr |= NAND_ADDR_CLE;
+ if (ctrl & NAND_ALE)
+ nandaddr |= NAND_ADDR_ALE;
+
+ this->IO_ADDR_W = (void __iomem *) nandaddr;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static struct platform_nand_data falcon_flash_nand_data = {
+ .chip = {
+ .nr_chips = 1,
+ .chip_delay = 25,
+ .part_probe_types = part_probes,
+ },
+ .ctrl = {
+ .cmd_ctrl = falcon_hwcontrol,
+ .dev_ready = falcon_nand_ready,
+ }
+};
+
+static struct resource ltq_nand_res =
+ MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
+
+static struct platform_device ltq_flash_nand = {
+ .name = "gen_nand",
+ .id = -1,
+ .num_resources = 1,
+ .resource = <q_nand_res,
+ .dev = {
+ .platform_data = &falcon_flash_nand_data,
+ },
+};
+
+void __init
+falcon_register_nand(void)
+{
+ platform_device_register(<q_flash_nand);
+}
diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
new file mode 100644
index 0000000..e802a7c
--- /dev/null
+++ b/arch/mips/lantiq/falcon/devices.h
@@ -0,0 +1,18 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _FALCON_DEVICES_H__
+#define _FALCON_DEVICES_H__
+
+#include "../devices.h"
+
+extern void falcon_register_nand(void);
+
+#endif
diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
new file mode 100644
index 0000000..b50d6f9
--- /dev/null
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -0,0 +1,93 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <lantiq_soc.h>
+
+#include "devices.h"
+
+#include "../prom.h"
+
+#define SOC_FALCON "Falcon"
+#define SOC_FALCON_D "Falcon-D"
+#define SOC_FALCON_V "Falcon-V"
+#define SOC_FALCON_M "Falcon-M"
+
+#define PART_SHIFT 12
+#define PART_MASK 0x0FFFF000
+#define REV_SHIFT 28
+#define REV_MASK 0xF0000000
+#define SREV_SHIFT 22
+#define SREV_MASK 0x03C00000
+#define TYPE_SHIFT 26
+#define TYPE_MASK 0x3C000000
+
+#define MUXC_SIF_RX_PIN 112
+#define MUXC_SIF_TX_PIN 113
+
+/* this parameter allows us enable/disable asc1 via commandline */
+static int register_asc1;
+static int __init
+ltq_parse_asc1(char *p)
+{
+ register_asc1 = 1;
+ return 0;
+}
+__setup("use_asc1", ltq_parse_asc1);
+
+void __init
+ltq_soc_setup(void)
+{
+ ltq_register_asc(0);
+ ltq_register_wdt();
+ falcon_register_gpio();
+ if (register_asc1) {
+ ltq_register_asc(1);
+ if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
+ pr_err("failed to request asc1-rx");
+ if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
+ pr_err("failed to request asc1-tx");
+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
+ }
+}
+
+void __init
+ltq_soc_detect(struct ltq_soc_info *i)
+{
+ u32 type;
+ i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
+ i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
+ i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
+ sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
+ i->rev & 0x7, (i->srev & 0x3) + 1);
+
+ switch (i->partnum) {
+ case SOC_ID_FALCON:
+ type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
+ switch (type) {
+ case 0:
+ i->name = SOC_FALCON_D;
+ break;
+ case 1:
+ i->name = SOC_FALCON_V;
+ break;
+ case 2:
+ i->name = SOC_FALCON_M;
+ break;
+ default:
+ i->name = SOC_FALCON;
+ break;
+ }
+ i->type = SOC_TYPE_FALCON;
+ break;
+
+ default:
+ unreachable();
+ break;
+ }
+}
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
new file mode 100644
index 0000000..aa7a770
--- /dev/null
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -0,0 +1,91 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+#include <linux/export.h>
+
+#include <lantiq_soc.h>
+
+/* CPU0 Reset Source Register */
+#define LTQ_SYS1_CPU0RS 0x0040
+/* reset cause mask */
+#define LTQ_CPU0RS_MASK 0x0003
+
+int
+ltq_reset_cause(void)
+{
+ return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
+}
+EXPORT_SYMBOL_GPL(ltq_reset_cause);
+
+#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
+#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
+#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
+#define BOOT_PW1 0x4C545100
+#define BOOT_PW2 0x0051544C
+
+#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
+#define WDT_PW1 0x00BE0000
+#define WDT_PW2 0x00DC0000
+
+static void
+ltq_machine_restart(char *command)
+{
+ pr_notice("System restart\n");
+ local_irq_disable();
+
+ /* reboot magic */
+ ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
+ ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
+ ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
+
+ /* watchdog magic */
+ ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
+ ltq_w32(WDT_PW2 |
+ (0x3 << 26) | /* PWL */
+ (0x2 << 24) | /* CLKDIV */
+ (0x1 << 31) | /* enable */
+ (1), /* reload */
+ (void *)WDT_REG_BASE);
+ /*
+ * Dont call unreachable(); here as we need to wait for the watchdog
+ * to trigger.
+ */
+ do {} while(1);
+}
+
+static void
+ltq_machine_halt(void)
+{
+ pr_notice("System halted.\n");
+ local_irq_disable();
+ unreachable();
+}
+
+static void
+ltq_machine_power_off(void)
+{
+ pr_notice("Please turn off the power now.\n");
+ local_irq_disable();
+ unreachable();
+}
+
+static int __init
+mips_reboot_setup(void)
+{
+ _machine_restart = ltq_machine_restart;
+ _machine_halt = ltq_machine_halt;
+ pm_power_off = ltq_machine_power_off;
+ return 0;
+}
+
+arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
new file mode 100644
index 0000000..905a142
--- /dev/null
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -0,0 +1,183 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/ioport.h>
+#include <linux/export.h>
+#include <asm/delay.h>
+
+#include <lantiq_soc.h>
+
+#include "devices.h"
+
+/* infrastructure control register */
+#define SYS1_INFRAC 0x00bc
+/* Configuration fuses for drivers and pll */
+#define STATUS_CONFIG 0x0040
+
+/* GPE frequency selection */
+#define GPPC_OFFSET 24
+#define GPEFREQ_MASK 0x00000C0
+#define GPEFREQ_OFFSET 10
+/* Clock status register */
+#define LTQ_SYSCTL_CLKS 0x0000
+/* Clock enable register */
+#define LTQ_SYSCTL_CLKEN 0x0004
+/* Clock clear register */
+#define LTQ_SYSCTL_CLKCLR 0x0008
+/* Activation Status Register */
+#define LTQ_SYSCTL_ACTS 0x0020
+/* Activation Register */
+#define LTQ_SYSCTL_ACT 0x0024
+/* Deactivation Register */
+#define LTQ_SYSCTL_DEACT 0x0028
+/* reboot Register */
+#define LTQ_SYSCTL_RBT 0x002c
+
+static struct resource ltq_sysctl_res[] = {
+ MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
+ MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
+ MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
+};
+
+static struct resource ltq_status_res =
+ MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
+static struct resource ltq_ebu_res =
+ MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
+
+static void __iomem *ltq_sysctl[3];
+static void __iomem *ltq_status_membase;
+void __iomem *ltq_sys1_membase;
+void __iomem *ltq_ebu_membase;
+
+#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y))
+#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x))
+#define ltq_reg_w32_mask(m, clear, set, reg) \
+ ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
+
+#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y))
+#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x))
+
+static inline void
+ltq_sysctl_wait(int module, unsigned int mask,
+ unsigned int test, unsigned int reg)
+{
+ int err = 1000000;
+
+ do {} while (--err && ((ltq_reg_r32(module, reg)
+ & mask) != test));
+ if (!err)
+ pr_err("module de/activation failed %d %08X %08X\n",
+ module, mask, test);
+}
+
+void
+ltq_sysctl_activate(int module, unsigned int mask)
+{
+ if (module > SYSCTL_SYSGPE)
+ return;
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+}
+EXPORT_SYMBOL(ltq_sysctl_activate);
+
+void
+ltq_sysctl_deactivate(int module, unsigned int mask)
+{
+ if (module > SYSCTL_SYSGPE)
+ return;
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
+ ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS);
+}
+EXPORT_SYMBOL(ltq_sysctl_deactivate);
+
+void
+ltq_sysctl_clken(int module, unsigned int mask)
+{
+ if (module > SYSCTL_SYSGPE)
+ return;
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS);
+}
+EXPORT_SYMBOL(ltq_sysctl_clken);
+
+void
+ltq_sysctl_clkdis(int module, unsigned int mask)
+{
+ if (module > SYSCTL_SYSGPE)
+ return;
+
+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
+ ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS);
+}
+EXPORT_SYMBOL(ltq_sysctl_clkdis);
+
+void
+ltq_sysctl_reboot(int module, unsigned int mask)
+{
+ unsigned int act;
+
+ if (module > SYSCTL_SYSGPE)
+ return;
+
+ act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
+ if ((~act & mask) != 0)
+ ltq_sysctl_activate(module, ~act & mask);
+ ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS);
+}
+EXPORT_SYMBOL(ltq_sysctl_reboot);
+
+/* enable the ONU core */
+static void
+ltq_gpe_enable(void)
+{
+ unsigned int freq;
+ unsigned int status;
+
+ /* if if the clock is already enabled */
+ status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
+ if (status & (1 << (GPPC_OFFSET + 1)))
+ return;
+
+ if (ltq_status_r32(STATUS_CONFIG) == 0)
+ freq = 1; /* use 625MHz on unfused chip */
+ else
+ freq = (ltq_status_r32(STATUS_CONFIG) &
+ GPEFREQ_MASK) >>
+ GPEFREQ_OFFSET;
+
+ /* apply new frequency */
+ ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
+ freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
+ udelay(1);
+
+ /* enable new frequency */
+ ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
+ udelay(1);
+}
+
+void __init
+ltq_soc_init(void)
+{
+ int i;
+
+ for (i = 0; i < 3; i++)
+ ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]);
+
+ ltq_sys1_membase = ltq_sysctl[0];
+ ltq_status_membase = ltq_remap_resource(<q_status_res);
+ ltq_ebu_membase = ltq_remap_resource(<q_ebu_res);
+
+ ltq_gpe_enable();
+}
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 05/17] MIPS: lantiq: add support for FALC-ON GPIOs
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (2 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 04/17] MIPS: lantiq: add basic support for FALC-ON John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-11 20:44 ` [PATCH RESEND 06/17] MIPS: lantiq: add support for the EASY98000 evaluation board John Crispin
` (12 subsequent siblings)
16 siblings, 0 replies; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds
the new driver.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/falcon/Makefile | 2 +-
arch/mips/lantiq/falcon/devices.c | 41 ++++
arch/mips/lantiq/falcon/devices.h | 2 +
arch/mips/lantiq/falcon/gpio.c | 399 +++++++++++++++++++++++++++++++++++++
4 files changed, 443 insertions(+), 1 deletions(-)
create mode 100644 arch/mips/lantiq/falcon/gpio.c
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index e9c7455..de72209 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1 +1 @@
-obj-y := clk.o prom.o reset.o sysctrl.o devices.o
+obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
index c4606f2..4f47b44 100644
--- a/arch/mips/lantiq/falcon/devices.c
+++ b/arch/mips/lantiq/falcon/devices.c
@@ -9,6 +9,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/nand.h>
+#include <linux/gpio.h>
#include <lantiq_soc.h>
@@ -85,3 +86,43 @@ falcon_register_nand(void)
{
platform_device_register(<q_flash_nand);
}
+
+/* gpio */
+#define DECLARE_GPIO_RES(port) \
+static struct resource falcon_gpio ## port ## _res[] = { \
+ MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \
+ LTQ_GPIO ## port ## _SIZE), \
+ MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \
+ LTQ_PADCTRL ## port ## _SIZE), \
+ IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \
+}
+DECLARE_GPIO_RES(0);
+DECLARE_GPIO_RES(1);
+DECLARE_GPIO_RES(2);
+DECLARE_GPIO_RES(3);
+DECLARE_GPIO_RES(4);
+
+void __init
+falcon_register_gpio(void)
+{
+ platform_device_register_simple("falcon_gpio", 0,
+ falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res));
+ platform_device_register_simple("falcon_gpio", 1,
+ falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
+ platform_device_register_simple("falcon_gpio", 2,
+ falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
+ ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
+ ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
+}
+
+void __init
+falcon_register_gpio_extra(void)
+{
+ platform_device_register_simple("falcon_gpio", 3,
+ falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
+ platform_device_register_simple("falcon_gpio", 4,
+ falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
+ ltq_sysctl_activate(SYSCTL_SYS1,
+ ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
+}
diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
index e802a7c..18be8b6 100644
--- a/arch/mips/lantiq/falcon/devices.h
+++ b/arch/mips/lantiq/falcon/devices.h
@@ -14,5 +14,7 @@
#include "../devices.h"
extern void falcon_register_nand(void);
+extern void falcon_register_gpio(void);
+extern void falcon_register_gpio_extra(void);
#endif
diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
new file mode 100644
index 0000000..28f8639
--- /dev/null
+++ b/arch/mips/lantiq/falcon/gpio.c
@@ -0,0 +1,399 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+
+#include <lantiq_soc.h>
+
+/* Multiplexer Control Register */
+#define LTQ_PADC_MUX(x) (x * 0x4)
+/* Pad Control Availability Register */
+#define LTQ_PADC_AVAIL 0x000000F0
+
+/* Data Output Register */
+#define LTQ_GPIO_OUT 0x00000000
+/* Data Input Register */
+#define LTQ_GPIO_IN 0x00000004
+/* Direction Register */
+#define LTQ_GPIO_DIR 0x00000008
+/* External Interrupt Control Register 0 */
+#define LTQ_GPIO_EXINTCR0 0x00000018
+/* External Interrupt Control Register 1 */
+#define LTQ_GPIO_EXINTCR1 0x0000001C
+/* IRN Capture Register */
+#define LTQ_GPIO_IRNCR 0x00000020
+/* IRN Interrupt Configuration Register */
+#define LTQ_GPIO_IRNCFG 0x0000002C
+/* IRN Interrupt Enable Set Register */
+#define LTQ_GPIO_IRNRNSET 0x00000030
+/* IRN Interrupt Enable Clear Register */
+#define LTQ_GPIO_IRNENCLR 0x00000034
+/* Output Set Register */
+#define LTQ_GPIO_OUTSET 0x00000040
+/* Output Cler Register */
+#define LTQ_GPIO_OUTCLR 0x00000044
+/* Direction Clear Register */
+#define LTQ_GPIO_DIRSET 0x00000048
+/* Direction Set Register */
+#define LTQ_GPIO_DIRCLR 0x0000004C
+
+/* turn a gpio_chip into a falcon_gpio_port */
+#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
+/* turn a irq_data into a falcon_gpio_port */
+#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
+
+#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg)
+#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg)
+#define ltq_pad_w32_mask(c, clear, set, reg) \
+ ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
+
+#define ltq_port_r32(p, reg) ltq_r32(p->port + reg)
+#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg)
+#define ltq_port_w32_mask(p, clear, set, reg) \
+ ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
+
+#define MAX_PORTS 5
+#define PINS_PER_PORT 32
+
+struct falcon_gpio_port {
+ struct gpio_chip gpio_chip;
+ void __iomem *pad;
+ void __iomem *port;
+ unsigned int irq_base;
+ unsigned int chained_irq;
+};
+
+static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
+
+int gpio_to_irq(unsigned int gpio)
+{
+ return __gpio_to_irq(gpio);
+}
+EXPORT_SYMBOL(gpio_to_irq);
+
+int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
+{
+ int port = pin / 100;
+ int offset = pin % 100;
+ struct falcon_gpio_port *gpio_port;
+
+ if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
+ return -EINVAL;
+
+ gpio_port = <q_gpio_port[port];
+ ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
+
+ return 0;
+}
+EXPORT_SYMBOL(ltq_gpio_mux_set);
+
+int ltq_gpio_request(unsigned int pin, unsigned int mux,
+ unsigned int dir, const char *name)
+{
+ int port = pin / 100;
+ int offset = pin % 100;
+
+ if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
+ return -EINVAL;
+
+ if (gpio_request(pin, name)) {
+ pr_err("failed to setup lantiq gpio: %s\n", name);
+ return -EBUSY;
+ }
+
+ if (dir)
+ gpio_direction_output(pin, 1);
+ else
+ gpio_direction_input(pin);
+
+ return ltq_gpio_mux_set(pin, mux);
+}
+EXPORT_SYMBOL(ltq_gpio_request);
+
+static int
+falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+{
+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
+
+ return 0;
+}
+
+static void
+falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
+{
+ if (value)
+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
+ else
+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
+}
+
+static int
+falcon_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset, int value)
+{
+ falcon_gpio_set(chip, offset, value);
+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
+
+ return 0;
+}
+
+static int
+falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
+ else
+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
+}
+
+static int
+falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
+ return -EBUSY;
+ /* switch on gpio function */
+ ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
+ return 0;
+ }
+
+ return -ENODEV;
+}
+
+static void
+falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
+ return;
+ /* switch off gpio function */
+ ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
+ }
+}
+
+static int
+falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ return ctop(chip)->irq_base + offset;
+}
+
+static void
+falcon_gpio_disable_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
+}
+
+static void
+falcon_gpio_enable_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
+ /* switch on gpio function */
+ ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
+
+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
+}
+
+static void
+falcon_gpio_ack_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
+}
+
+static void
+falcon_gpio_mask_and_ack_irq(struct irq_data *d)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+
+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
+}
+
+static struct irq_chip falcon_gpio_irq_chip;
+static int
+falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
+{
+ unsigned int offset = d->irq - itop(d)->irq_base;
+ unsigned int mask = 1 << offset;
+
+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
+ return 0;
+
+ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
+ /* level triggered */
+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
+ irq_set_chip_and_handler_name(d->irq,
+ &falcon_gpio_irq_chip, handle_level_irq, "mux");
+ } else {
+ /* edge triggered */
+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
+ irq_set_chip_and_handler_name(d->irq,
+ &falcon_gpio_irq_chip, handle_simple_irq, "mux");
+ }
+
+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
+ } else {
+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
+ /* positive logic: rising edge, high level */
+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
+ else
+ /* negative logic: falling edge, low level */
+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
+ }
+
+ return gpio_direction_input(itop(d)->gpio_chip.base + offset);
+}
+
+static void
+falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
+ unsigned long irncr;
+ int offset;
+
+ /* acknowledge interrupt */
+ irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
+ ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
+
+ desc->irq_data.chip->irq_ack(&desc->irq_data);
+
+ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
+ generic_handle_irq(gpio_port->irq_base + offset);
+}
+
+static struct irq_chip falcon_gpio_irq_chip = {
+ .name = "gpio_irq_mux",
+ .irq_mask = falcon_gpio_disable_irq,
+ .irq_unmask = falcon_gpio_enable_irq,
+ .irq_ack = falcon_gpio_ack_irq,
+ .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
+ .irq_set_type = falcon_gpio_irq_type,
+};
+
+static struct irqaction gpio_cascade = {
+ .handler = no_action,
+ .flags = IRQF_DISABLED,
+ .name = "gpio_cascade",
+};
+
+static int
+falcon_gpio_probe(struct platform_device *pdev)
+{
+ struct falcon_gpio_port *gpio_port;
+ int ret, i;
+ struct resource *gpiores, *padres;
+ int irq;
+
+ if (pdev->id >= MAX_PORTS)
+ return -ENODEV;
+
+ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ irq = platform_get_irq(pdev, 0);
+ if (!gpiores || !padres)
+ return -ENODEV;
+
+ gpio_port = <q_gpio_port[pdev->id];
+ gpio_port->gpio_chip.label = "falcon-gpio";
+ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
+ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
+ gpio_port->gpio_chip.get = falcon_gpio_get;
+ gpio_port->gpio_chip.set = falcon_gpio_set;
+ gpio_port->gpio_chip.request = falcon_gpio_request;
+ gpio_port->gpio_chip.free = falcon_gpio_free;
+ gpio_port->gpio_chip.base = 100 * pdev->id;
+ gpio_port->gpio_chip.ngpio = 32;
+ gpio_port->gpio_chip.dev = &pdev->dev;
+
+ gpio_port->port = ltq_remap_resource(gpiores);
+ gpio_port->pad = ltq_remap_resource(padres);
+
+ if (!gpio_port->port || !gpio_port->pad) {
+ dev_err(&pdev->dev, "Could not map io ranges\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ if (irq > 0) {
+ /* irq_chip support */
+ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
+ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
+
+ for (i = 0; i < 32; i++) {
+ irq_set_chip_and_handler_name(gpio_port->irq_base + i,
+ &falcon_gpio_irq_chip, handle_simple_irq,
+ "mux");
+ irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
+ /* set to negative logic (falling edge, low level) */
+ ltq_port_w32_mask(gpio_port, 0, 1 << i,
+ LTQ_GPIO_EXINTCR0);
+ }
+
+ gpio_port->chained_irq = irq;
+ setup_irq(irq, &gpio_cascade);
+ irq_set_handler_data(irq, gpio_port);
+ irq_set_chained_handler(irq, falcon_gpio_irq_handler);
+ }
+
+ ret = gpiochip_add(&gpio_port->gpio_chip);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
+ pdev->id, ret);
+ goto err;
+ }
+ platform_set_drvdata(pdev, gpio_port);
+ return ret;
+
+err:
+ dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
+ if (gpiores)
+ release_resource(gpiores);
+ if (padres)
+ release_resource(padres);
+
+ if (gpio_port->port)
+ iounmap(gpio_port->port);
+ if (gpio_port->pad)
+ iounmap(gpio_port->pad);
+ return ret;
+}
+
+static struct platform_driver falcon_gpio_driver = {
+ .probe = falcon_gpio_probe,
+ .driver = {
+ .name = "falcon_gpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+int __init
+falcon_gpio_init(void)
+{
+ int ret;
+
+ pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
+ ret = platform_driver_register(&falcon_gpio_driver);
+ if (ret)
+ pr_err("falcon_gpio: Error registering platform driver!");
+ return ret;
+}
+
+postcore_initcall(falcon_gpio_init);
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 06/17] MIPS: lantiq: add support for the EASY98000 evaluation board
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (3 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 05/17] MIPS: lantiq: add support for FALC-ON GPIOs John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:20 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 07/17] MIPS: lantiq: fix early printk John Crispin
` (11 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
This patch adds the machine code for the EASY9800 evaluation board.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/falcon/Kconfig | 11 +++
arch/mips/lantiq/falcon/Makefile | 1 +
arch/mips/lantiq/falcon/mach-easy98000.c | 110 ++++++++++++++++++++++++++++++
arch/mips/lantiq/machtypes.h | 5 ++
4 files changed, 127 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/lantiq/falcon/Kconfig
create mode 100644 arch/mips/lantiq/falcon/mach-easy98000.c
diff --git a/arch/mips/lantiq/falcon/Kconfig b/arch/mips/lantiq/falcon/Kconfig
new file mode 100644
index 0000000..03e999d
--- /dev/null
+++ b/arch/mips/lantiq/falcon/Kconfig
@@ -0,0 +1,11 @@
+if SOC_FALCON
+
+menu "MIPS Machine"
+
+config LANTIQ_MACH_EASY98000
+ bool "Easy98000"
+ default y
+
+endmenu
+
+endif
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
index de72209..56b22eb 100644
--- a/arch/mips/lantiq/falcon/Makefile
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -1 +1,2 @@
obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c
new file mode 100644
index 0000000..361b8f0
--- /dev/null
+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
@@ -0,0 +1,110 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/spi/eeprom.h>
+
+#include "../machtypes.h"
+
+#include "devices.h"
+
+static struct mtd_partition easy98000_nor_partitions[] = {
+ {
+ .name = "uboot",
+ .offset = 0x0,
+ .size = 0x40000,
+ },
+ {
+ .name = "uboot_env",
+ .offset = 0x40000,
+ .size = 0x40000, /* 2 sectors for redundant env. */
+ },
+ {
+ .name = "linux",
+ .offset = 0x80000,
+ .size = 0xF80000, /* map only 16 MiB */
+ },
+};
+
+struct physmap_flash_data easy98000_nor_flash_data = {
+ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions),
+ .parts = easy98000_nor_partitions,
+};
+
+/* setup gpio based spi bus/device for access to the eeprom on the board */
+#define SPI_GPIO_MRST 102
+#define SPI_GPIO_MTSR 103
+#define SPI_GPIO_CLK 104
+#define SPI_GPIO_CS0 105
+#define SPI_GPIO_CS1 106
+#define SPI_GPIO_BUS_NUM 1
+
+static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
+ .sck = SPI_GPIO_CLK,
+ .mosi = SPI_GPIO_MTSR,
+ .miso = SPI_GPIO_MRST,
+ .num_chipselect = 2,
+};
+
+static struct platform_device easy98000_spi_gpio_device = {
+ .name = "spi_gpio",
+ .id = SPI_GPIO_BUS_NUM,
+ .dev.platform_data = &easy98000_spi_gpio_data,
+};
+
+static struct spi_eeprom at25160n = {
+ .byte_len = 16 * 1024 / 8,
+ .name = "at25160n",
+ .page_size = 32,
+ .flags = EE_ADDR2,
+};
+
+static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
+ .modalias = "at25",
+ .bus_num = SPI_GPIO_BUS_NUM,
+ .max_speed_hz = 1000 * 1000,
+ .mode = SPI_MODE_3,
+ .chip_select = 1,
+ .controller_data = (void *) SPI_GPIO_CS1,
+ .platform_data = &at25160n,
+};
+
+static void __init
+easy98000_init_common(void)
+{
+ spi_register_board_info(&easy98000_spi_gpio_devices, 1);
+ platform_device_register(&easy98000_spi_gpio_device);
+}
+
+static void __init
+easy98000_init(void)
+{
+ easy98000_init_common();
+ ltq_register_nor(&easy98000_nor_flash_data);
+}
+
+static void __init
+easy98000nand_init(void)
+{
+ easy98000_init_common();
+ falcon_register_nand();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_EASY98000,
+ "EASY98000",
+ "EASY98000 Eval Board",
+ easy98000_init);
+
+MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
+ "EASY98000NAND",
+ "EASY98000 Eval Board (NAND Flash)",
+ easy98000nand_init);
diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h
index 7e01b8c..dfc6af7 100644
--- a/arch/mips/lantiq/machtypes.h
+++ b/arch/mips/lantiq/machtypes.h
@@ -15,6 +15,11 @@ enum lantiq_mach_type {
LTQ_MACH_GENERIC = 0,
LTQ_MACH_EASY50712, /* Danube evaluation board */
LTQ_MACH_EASY50601, /* Amazon SE evaluation board */
+
+ /* FALCON */
+ LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */
+ LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */
+ LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */
};
#endif
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 07/17] MIPS: lantiq: fix early printk
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (4 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 06/17] MIPS: lantiq: add support for the EASY98000 evaluation board John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:20 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 08/17] MIPS: lantiq: fix cmdline parsing John Crispin
` (10 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
The code was using a 32bit write operations in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. This patch
changes the memory access to 8bit.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 ++++++
arch/mips/lantiq/early_printk.c | 14 ++++++++------
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index a6521ec..c8024e3 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -34,6 +34,12 @@
#define LTQ_ASC1_BASE_ADDR 0x1E100C00
#define LTQ_ASC_SIZE 0x400
+/*
+ * during early_printk no ioremap is possible
+ * lets use KSEG1 instead
+ */
+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+
/* RCU - reset control unit */
#define LTQ_RCU_BASE_ADDR 0x1F203000
#define LTQ_RCU_SIZE 0x1000
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
index 972e05f..5089075 100644
--- a/arch/mips/lantiq/early_printk.c
+++ b/arch/mips/lantiq/early_printk.c
@@ -12,11 +12,13 @@
#include <lantiq.h>
#include <lantiq_soc.h>
-/* no ioremap possible at this early stage, lets use KSEG1 instead */
-#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
#define ASC_BUF 1024
-#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048))
-#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020))
+#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))
+#ifdef __BIG_ENDIAN
+#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
+#else
+#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))
+#endif
#define TXMASK 0x3F00
#define TXOFFSET 8
@@ -27,7 +29,7 @@ void prom_putchar(char c)
local_irq_save(flags);
do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
if (c == '\n')
- ltq_w32('\r', LTQ_ASC_TBUF);
- ltq_w32(c, LTQ_ASC_TBUF);
+ ltq_w8('\r', LTQ_ASC_TBUF);
+ ltq_w8(c, LTQ_ASC_TBUF);
local_irq_restore(flags);
}
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 08/17] MIPS: lantiq: fix cmdline parsing
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (5 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 07/17] MIPS: lantiq: fix early printk John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:20 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 09/17] MIPS: lantiq: fix STP gpio groups John Crispin
` (9 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Thomas Langer
The code tested if the KSEG1 mapped address of argv was != 0. We need to use
CPHYSADDR instead to make the conditional actually work.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/prom.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 528e205..ee63a33 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -49,10 +49,12 @@ static void __init prom_init_cmdline(void)
char **argv = (char **) KSEG1ADDR(fw_arg1);
int i;
+ arcs_cmdline[0] = '\0';
+
for (i = 0; i < argc; i++) {
- char *p = (char *) KSEG1ADDR(argv[i]);
+ char *p = (char *) KSEG1ADDR(argv[i]);
- if (p && *p) {
+ if (CPHYSADDR(p) && *p) {
strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
}
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 09/17] MIPS: lantiq: fix STP gpio groups
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (6 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 08/17] MIPS: lantiq: fix cmdline parsing John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:20 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 10/17] MIPS: lantiq: fix pull gpio up resistors usage John Crispin
` (8 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Matti Laakso
The STP engine has 3 groups of 8 pins. Only the first was activated by default.
This patch activates the 2 missing groups.
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/gpio_stp.c | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index 2c78660..cb6f170 100644
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -35,6 +35,8 @@
#define LTQ_STP_ADSL_SRC (3 << 24)
#define LTQ_STP_GROUP0 (1 << 0)
+#define LTQ_STP_GROUP1 (1 << 1)
+#define LTQ_STP_GROUP2 (1 << 2)
#define LTQ_STP_RISING 0
#define LTQ_STP_FALLING (1 << 26)
@@ -93,8 +95,9 @@ static int ltq_stp_hw_init(void)
/* rising or falling edge */
ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
- /* per default stp 15-0 are set */
- ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
+ /* enable all three led groups */
+ ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2,
+ LTQ_STP_CON1);
/* stp are update periodically by the FPI bus */
ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 10/17] MIPS: lantiq: fix pull gpio up resistors usage
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (7 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 09/17] MIPS: lantiq: fix STP gpio groups John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:20 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 11/17] MIPS: lantiq: add default configs John Crispin
` (7 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Matti Laakso
The register that enables a gpios internal pullups was not used. This patch
makes sure the pullups are activated correctly.
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/xway/gpio.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index f204f6c..14ff7c7 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -21,6 +21,8 @@
#define LTQ_GPIO_ALTSEL0 0x0C
#define LTQ_GPIO_ALTSEL1 0x10
#define LTQ_GPIO_OD 0x14
+#define LTQ_GPIO_PUDSEL 0x1C
+#define LTQ_GPIO_PUDEN 0x20
#define PINS_PER_PORT 16
#define MAX_PORTS 3
@@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
return 0;
}
@@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip,
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset);
+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset);
ltq_gpio_set(chip, offset, value);
return 0;
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 11/17] MIPS: lantiq: add default configs
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (8 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 10/17] MIPS: lantiq: fix pull gpio up resistors usage John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:20 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 12/17] MAINTAINERS: add entry for Lantiq related files John Crispin
` (6 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
This patch adds the default config for 3 Lantiq SoCs
* Danube/AR9 (xway)
* Amazon-SE
* Falc-ON
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/configs/ase_defconfig | 80 ++++++++++++++++++++++++++++++++++
arch/mips/configs/falcon_defconfig | 83 ++++++++++++++++++++++++++++++++++++
arch/mips/configs/xway_defconfig | 81 +++++++++++++++++++++++++++++++++++
3 files changed, 244 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/configs/ase_defconfig
create mode 100644 arch/mips/configs/falcon_defconfig
create mode 100644 arch/mips/configs/xway_defconfig
diff --git a/arch/mips/configs/ase_defconfig b/arch/mips/configs/ase_defconfig
new file mode 100644
index 0000000..04a6aa5
--- /dev/null
+++ b/arch/mips/configs/ase_defconfig
@@ -0,0 +1,80 @@
+CONFIG_LANTIQ=y
+CONFIG_SOC_AMAZON_SE=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_DEFAULT_HOSTNAME="amazon_se"
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
+# CONFIG_RD_GZIP is not set
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MISC_DEVICES=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_LANTIQ_ETOP=y
+CONFIG_PHYLIB=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_LANTIQ=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_LANTIQ_WDT=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/mips/configs/falcon_defconfig b/arch/mips/configs/falcon_defconfig
new file mode 100644
index 0000000..ab8f8e2
--- /dev/null
+++ b/arch/mips/configs/falcon_defconfig
@@ -0,0 +1,83 @@
+CONFIG_LANTIQ=y
+CONFIG_SOC_FALCON=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_DEFAULT_HOSTNAME="falcon"
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_M25P80=y
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT24=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_LANTIQ=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_FALCON=y
+CONFIG_SPI=y
+CONFIG_SPI_FALCON=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_WATCHDOG=y
+CONFIG_LANTIQ_WDT=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/mips/configs/xway_defconfig b/arch/mips/configs/xway_defconfig
new file mode 100644
index 0000000..461d58d
--- /dev/null
+++ b/arch/mips/configs/xway_defconfig
@@ -0,0 +1,81 @@
+CONFIG_LANTIQ=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_DEFAULT_HOSTNAME="danube"
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
+# CONFIG_RD_GZIP is not set
+CONFIG_RD_LZMA=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_PCI=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MISC_DEVICES=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_LANTIQ_ETOP=y
+CONFIG_PHYLIB=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_LANTIQ=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_LANTIQ_WDT=y
+# CONFIG_VGA_ARB is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 12/17] MAINTAINERS: add entry for Lantiq related files
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (9 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 11/17] MIPS: lantiq: add default configs John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-11 20:44 ` [PATCH RESEND 13/17] NET: MIPS: lantiq: make etop ethernet work on ase/ar9 John Crispin
` (5 subsequent siblings)
16 siblings, 0 replies; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
Adds new entry to MAINTAINERS file for Lantiq SoC related code.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
MAINTAINERS | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4475602..caf9d00 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4362,6 +4362,18 @@ S: Supported
F: Documentation/mips/
F: arch/mips/
+MIPS/LANTIQ
+M: John Crispin <blogic@openwrt.org>
+M: Thomas Langer <thomas.langer@lantiq.com>
+S: Maintained
+F: arch/mips/lantiq/*
+F: drivers/i2c/busses/i2c-falcon.c
+F: drivers/mtd/maps/lantiq-flash.c
+F: drivers/net/ethernet/lantiq_etop.c
+F: drivers/spi/spi-falcon.c
+F: drivers/tty/serial/lantiq.c
+F: drivers/watchdog/lantiq_wdt.c
+
MISCELLANEOUS MCA-SUPPORT
M: James Bottomley <James.Bottomley@HansenPartnership.com>
S: Maintained
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 13/17] NET: MIPS: lantiq: make etop ethernet work on ase/ar9
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (10 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 12/17] MAINTAINERS: add entry for Lantiq related files John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:21 ` Ralf Baechle
2012-01-11 20:44 ` [PATCH RESEND 14/17] NET: MIPS: lantiq: non existing phy was not handled gracefully John Crispin
` (4 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
Extend the driver to handle the different DMA channel layout for AR9 and
Amazon-SE SoCs. The patch also adds support for the integrated PHY found
on Amazon-SE and the gigabit switch found inside the AR9.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: David S. Miller <davem@davemloft.net>
---
.../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 22 +---
.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 10 ++
arch/mips/lantiq/xway/devices.c | 11 +-
arch/mips/lantiq/xway/mach-easy50601.c | 5 +
drivers/net/ethernet/lantiq_etop.c | 171 ++++++++++++++++++--
5 files changed, 179 insertions(+), 40 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index b4465a8..2a8d5ad 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -38,26 +38,8 @@
#define MIPS_CPU_TIMER_IRQ 7
-#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
-#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
-#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
-#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
-#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
-#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
-#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
-#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
-#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
-#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
-#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
-#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
-#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
-#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
-#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
-#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
-#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
-#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
-#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
-#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
+#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \
+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index c8024e3..763e163 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -82,6 +82,7 @@
#define LTQ_PMU_SIZE 0x1000
#define PMU_DMA 0x0020
+#define PMU_EPHY 0x0080
#define PMU_USB 0x8041
#define PMU_LED 0x0800
#define PMU_GPT 0x1000
@@ -93,6 +94,10 @@
#define LTQ_ETOP_BASE_ADDR 0x1E180000
#define LTQ_ETOP_SIZE 0x40000
+/* GBIT - gigabit switch */
+#define LTQ_GBIT_BASE_ADDR 0x1E108000
+#define LTQ_GBIT_SIZE 0x200
+
/* DMA */
#define LTQ_DMA_BASE_ADDR 0x1E104100
#define LTQ_DMA_SIZE 0x800
@@ -163,6 +168,11 @@ extern void ltq_pmu_enable(unsigned int module);
extern void ltq_pmu_disable(unsigned int module);
extern void ltq_cgu_enable(unsigned int clk);
+static inline int ltq_is_ase(void)
+{
+ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
+}
+
static inline int ltq_is_ar9(void)
{
return (ltq_get_soc_type() == SOC_TYPE_AR9);
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
index f97e565..eab4644d 100644
--- a/arch/mips/lantiq/xway/devices.c
+++ b/arch/mips/lantiq/xway/devices.c
@@ -74,18 +74,23 @@ void __init ltq_register_ase_asc(void)
}
/* ethernet */
-static struct resource ltq_etop_resources =
- MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
+static struct resource ltq_etop_resources[] = {
+ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE),
+ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE),
+};
static struct platform_device ltq_etop = {
.name = "ltq_etop",
- .resource = <q_etop_resources,
+ .resource = ltq_etop_resources,
.num_resources = 1,
};
void __init
ltq_register_etop(struct ltq_eth_data *eth)
{
+ /* only register the gphy on socs that have one */
+ if (ltq_is_ar9() | ltq_is_vr9())
+ ltq_etop.num_resources = 2;
if (eth) {
ltq_etop.dev.platform_data = eth;
platform_device_register(<q_etop);
diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c
index d5aaf63..16d65e0 100644
--- a/arch/mips/lantiq/xway/mach-easy50601.c
+++ b/arch/mips/lantiq/xway/mach-easy50601.c
@@ -46,9 +46,14 @@ static struct physmap_flash_data easy50601_flash_data = {
.parts = easy50601_partitions,
};
+static struct ltq_eth_data ltq_eth_data = {
+ .mii_mode = -1, /* use EPHY */
+};
+
static void __init easy50601_init(void)
{
ltq_register_nor(&easy50601_flash_data);
+ ltq_register_etop(<q_eth_data);
}
MIPS_MACHINE(LTQ_MACH_EASY50601,
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 0b3567a..d3d4931 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -71,10 +71,43 @@
#define ETOP_MII_REVERSE 0xe
#define ETOP_PLEN_UNDER 0x40
#define ETOP_CGEN 0x800
-
-/* use 2 static channels for TX/RX */
+#define ETOP_CFG_MII0 0x01
+
+#define LTQ_GBIT_MDIO_CTL 0xCC
+#define LTQ_GBIT_MDIO_DATA 0xd0
+#define LTQ_GBIT_GCTL0 0x68
+#define LTQ_GBIT_PMAC_HD_CTL 0x8c
+#define LTQ_GBIT_P0_CTL 0x4
+#define LTQ_GBIT_PMAC_RX_IPG 0xa8
+
+#define PMAC_HD_CTL_AS (1 << 19)
+#define PMAC_HD_CTL_RXSH (1 << 22)
+
+/* Switch Enable (0=disable, 1=enable) */
+#define GCTL0_SE 0x80000000
+/* Disable MDIO auto polling (0=disable, 1=enable) */
+#define PX_CTL_DMDIO 0x00400000
+
+/* register information for the gbit's MDIO bus */
+#define MDIO_XR9_REQUEST 0x00008000
+#define MDIO_XR9_READ 0x00000800
+#define MDIO_XR9_WRITE 0x00000400
+#define MDIO_XR9_REG_MASK 0x1f
+#define MDIO_XR9_ADDR_MASK 0x1f
+#define MDIO_XR9_RD_MASK 0xffff
+#define MDIO_XR9_REG_OFFSET 0
+#define MDIO_XR9_ADDR_OFFSET 5
+#define MDIO_XR9_WR_OFFSET 16
+
+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
+#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9())
+
+/* use 2 static channels for TX/RX
+ depending on the SoC we need to use different DMA channels for ethernet */
#define LTQ_ETOP_TX_CHANNEL 1
-#define LTQ_ETOP_RX_CHANNEL 6
+#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \
+ ((ltq_has_gbit()) ? (0) : (6)))
+
#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
@@ -83,9 +116,15 @@
#define ltq_etop_w32_mask(x, y, z) \
ltq_w32_mask(x, y, ltq_etop_membase + (z))
+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
+#define ltq_gbit_w32_mask(x, y, z) \
+ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
+
#define DRV_VERSION "1.0"
static void __iomem *ltq_etop_membase;
+static void __iomem *ltq_gbit_membase;
struct ltq_etop_chan {
int idx;
@@ -110,6 +149,9 @@ struct ltq_etop_priv {
spinlock_t lock;
};
+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
+ int phy_reg, u16 phy_data);
+
static int
ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
{
@@ -211,7 +253,7 @@ static irqreturn_t
ltq_etop_dma_irq(int irq, void *_priv)
{
struct ltq_etop_priv *priv = _priv;
- int ch = irq - LTQ_DMA_CH0_INT;
+ int ch = irq - LTQ_DMA_ETOP;
napi_schedule(&priv->ch[ch].napi);
return IRQ_HANDLED;
@@ -244,15 +286,43 @@ ltq_etop_hw_exit(struct net_device *dev)
ltq_etop_free_channel(dev, &priv->ch[i]);
}
+static void
+ltq_etop_gbit_init(void)
+{
+ ltq_pmu_enable(PMU_SWITCH);
+
+ ltq_gpio_request(42, 2, 1, "MDIO");
+ ltq_gpio_request(43, 2, 1, "MDC");
+
+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
+ /** Disable MDIO auto polling mode */
+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
+ /* set 1522 packet size */
+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
+ /* disable pmac & dmac headers */
+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
+ LTQ_GBIT_PMAC_HD_CTL);
+ /* Due to traffic halt when burst length 8,
+ replace default IPG value with 0x3B */
+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
+}
+
static int
ltq_etop_hw_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
+ unsigned int mii_mode = priv->pldata->mii_mode;
int i;
ltq_pmu_enable(PMU_PPE);
- switch (priv->pldata->mii_mode) {
+ if (ltq_has_gbit()) {
+ ltq_etop_gbit_init();
+ /* force the etops link to the gbit to MII */
+ mii_mode = PHY_INTERFACE_MODE_MII;
+ }
+
+ switch (mii_mode) {
case PHY_INTERFACE_MODE_RMII:
ltq_etop_w32_mask(ETOP_MII_MASK,
ETOP_MII_REVERSE, LTQ_ETOP_CFG);
@@ -264,6 +334,18 @@ ltq_etop_hw_init(struct net_device *dev)
break;
default:
+ if (ltq_is_ase()) {
+ ltq_pmu_enable(PMU_EPHY);
+ /* disable external MII */
+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
+ /* enable clock for internal PHY */
+ ltq_cgu_enable(CGU_EPHY);
+ /* we need to write this magic to the internal phy to
+ make it work */
+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
+ pr_info("Selected EPHY mode\n");
+ break;
+ }
netdev_err(dev, "unknown mii mode %d\n",
priv->pldata->mii_mode);
return -ENOTSUPP;
@@ -275,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev)
ltq_dma_init_port(DMA_PORT_ETOP);
for (i = 0; i < MAX_DMA_CHAN; i++) {
- int irq = LTQ_DMA_CH0_INT + i;
+ int irq = LTQ_DMA_ETOP + i;
struct ltq_etop_chan *ch = &priv->ch[i];
ch->idx = ch->dma.nr = i;
@@ -339,6 +421,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
};
static int
+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
+ int phy_reg, u16 phy_data)
+{
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
+ (phy_data << MDIO_XR9_WR_OFFSET) |
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
+
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ return 0;
+}
+
+static int
+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
+
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
+ ;
+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
+ return val;
+}
+
+static int
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
u32 val = MDIO_REQUEST |
@@ -379,14 +494,11 @@ ltq_etop_mdio_probe(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
struct phy_device *phydev = NULL;
- int phy_addr;
- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
- if (priv->mii_bus->phy_map[phy_addr]) {
- phydev = priv->mii_bus->phy_map[phy_addr];
- break;
- }
- }
+ if (ltq_is_ase())
+ phydev = priv->mii_bus->phy_map[8];
+ else
+ phydev = priv->mii_bus->phy_map[0];
if (!phydev) {
netdev_err(dev, "no PHY found\n");
@@ -408,6 +520,9 @@ ltq_etop_mdio_probe(struct net_device *dev)
| SUPPORTED_Autoneg
| SUPPORTED_MII
| SUPPORTED_TP);
+ if (ltq_has_gbit())
+ phydev->supported &= SUPPORTED_1000baseT_Half
+ | SUPPORTED_1000baseT_Full;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
@@ -433,8 +548,13 @@ ltq_etop_mdio_init(struct net_device *dev)
}
priv->mii_bus->priv = dev;
- priv->mii_bus->read = ltq_etop_mdio_rd;
- priv->mii_bus->write = ltq_etop_mdio_wr;
+ if (ltq_has_gbit()) {
+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
+ } else {
+ priv->mii_bus->read = ltq_etop_mdio_rd;
+ priv->mii_bus->write = ltq_etop_mdio_wr;
+ }
priv->mii_bus->name = "ltq_mii";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
@@ -524,9 +644,9 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
struct ltq_etop_priv *priv = netdev_priv(dev);
struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
- int len;
unsigned long flags;
u32 byte_offset;
+ int len;
len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
@@ -700,7 +820,7 @@ ltq_etop_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct ltq_etop_priv *priv;
- struct resource *res;
+ struct resource *res, *gbit_res;
int err;
int i;
@@ -728,6 +848,23 @@ ltq_etop_probe(struct platform_device *pdev)
goto err_out;
}
+ if (ltq_has_gbit()) {
+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!gbit_res) {
+ dev_err(&pdev->dev, "failed to get gbit resource\n");
+ err = -ENOENT;
+ goto err_out;
+ }
+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
+ gbit_res->start, resource_size(gbit_res));
+ if (!ltq_gbit_membase) {
+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
+ pdev->id);
+ err = -ENOMEM;
+ goto err_out;
+ }
+ }
+
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
strcpy(dev->name, "eth%d");
dev->netdev_ops = <q_eth_netdev_ops;
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 14/17] NET: MIPS: lantiq: non existing phy was not handled gracefully
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (11 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 13/17] NET: MIPS: lantiq: make etop ethernet work on ase/ar9 John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-11 20:44 ` [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq " John Crispin
` (3 subsequent siblings)
16 siblings, 0 replies; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
The code blindly assumed that that a PHY device was present causing a BadVA.
In addition the driver should not fail to load incase no PHY was found.
Instead we print the following line and continue with no attached PHY.
etop: mdio probe failed
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index d3d4931..9fd6779 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -612,7 +612,8 @@ ltq_etop_open(struct net_device *dev)
ltq_dma_open(&ch->dma);
napi_enable(&ch->napi);
}
- phy_start(priv->phydev);
+ if (priv->phydev)
+ phy_start(priv->phydev);
netif_tx_start_all_queues(dev);
return 0;
}
@@ -624,7 +625,8 @@ ltq_etop_stop(struct net_device *dev)
int i;
netif_tx_stop_all_queues(dev);
- phy_stop(priv->phydev);
+ if (priv->phydev)
+ phy_stop(priv->phydev);
for (i = 0; i < MAX_DMA_CHAN; i++) {
struct ltq_etop_chan *ch = &priv->ch[i];
@@ -770,9 +772,10 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_netdev;
ltq_etop_set_multicast_list(dev);
- err = ltq_etop_mdio_init(dev);
- if (err)
- goto err_netdev;
+ if (!ltq_etop_mdio_init(dev))
+ dev->ethtool_ops = <q_etop_ethtool_ops;
+ else
+ pr_warn("etop: mdio probe failed\n");;
return 0;
err_netdev:
@@ -868,7 +871,6 @@ ltq_etop_probe(struct platform_device *pdev)
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
strcpy(dev->name, "eth%d");
dev->netdev_ops = <q_eth_netdev_ops;
- dev->ethtool_ops = <q_etop_ethtool_ops;
priv = netdev_priv(dev);
priv->res = res;
priv->pldata = dev_get_platdata(&pdev->dev);
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq was not handled gracefully
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (12 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 14/17] NET: MIPS: lantiq: non existing phy was not handled gracefully John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-12 11:33 ` Sergei Shtylyov
2012-01-11 20:44 ` [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
` (2 subsequent siblings)
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
The return values of request_irq() were not checked leading to the following
error message.
drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init':
drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 9fd6779..659c868 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -312,6 +312,7 @@ ltq_etop_hw_init(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned int mii_mode = priv->pldata->mii_mode;
+ int err = 0;
int i;
ltq_pmu_enable(PMU_PPE);
@@ -356,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev)
ltq_dma_init_port(DMA_PORT_ETOP);
- for (i = 0; i < MAX_DMA_CHAN; i++) {
+ for (i = 0; i < MAX_DMA_CHAN && !err; i++) {
int irq = LTQ_DMA_ETOP + i;
struct ltq_etop_chan *ch = &priv->ch[i];
@@ -364,21 +365,22 @@ ltq_etop_hw_init(struct net_device *dev)
if (IS_TX(i)) {
ltq_dma_alloc_tx(&ch->dma);
- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+ err = request_irq(irq, ltq_etop_dma_irq, 0,
"etop_tx", priv);
} else if (IS_RX(i)) {
ltq_dma_alloc_rx(&ch->dma);
for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
ch->dma.desc++)
if (ltq_etop_alloc_skb(ch))
- return -ENOMEM;
+ err = -ENOMEM;
ch->dma.desc = 0;
- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
+ err = request_irq(irq, ltq_etop_dma_irq, 0,
"etop_rx", priv);
}
- ch->dma.irq = irq;
+ if (!err)
+ ch->dma.irq = irq;
}
- return 0;
+ return err;
}
static void
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq was not handled gracefully
2012-01-11 20:44 ` [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq " John Crispin
@ 2012-01-12 11:33 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2012-01-12 11:33 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, linux-mips
Hello.
On 12-01-2012 0:44, John Crispin wrote:
> The return values of request_irq() were not checked leading to the following
> error message.
> drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init':
> drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
> drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result
> Signed-off-by: John Crispin<blogic@openwrt.org>
> Acked-by: David S. Miller<davem@davemloft.net>
> ---
> drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------
> 1 files changed, 8 insertions(+), 6 deletions(-)
> diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
> index 9fd6779..659c868 100644
> --- a/drivers/net/ethernet/lantiq_etop.c
> +++ b/drivers/net/ethernet/lantiq_etop.c
[...]
> @@ -364,21 +365,22 @@ ltq_etop_hw_init(struct net_device *dev)
>
> if (IS_TX(i)) {
> ltq_dma_alloc_tx(&ch->dma);
> - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
> + err = request_irq(irq, ltq_etop_dma_irq, 0,
> "etop_tx", priv);
> } else if (IS_RX(i)) {
> ltq_dma_alloc_rx(&ch->dma);
> for (ch->dma.desc = 0; ch->dma.desc< LTQ_DESC_NUM;
> ch->dma.desc++)
> if (ltq_etop_alloc_skb(ch))
> - return -ENOMEM;
> + err = -ENOMEM;
This 'err' will get overwrtitten by subseuent request_irq().
> ch->dma.desc = 0;
> - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
> + err = request_irq(irq, ltq_etop_dma_irq, 0,
> "etop_rx", priv);
> }
> - ch->dma.irq = irq;
> + if (!err)
> + ch->dma.irq = irq;
> }
> - return 0;
> + return err;
> }
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (13 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 15/17] NET: MIPS: lantiq: return value of request_irq " John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-12 11:37 ` Sergei Shtylyov
2012-01-12 15:38 ` Sergei Shtylyov
2012-01-11 20:44 ` [PATCH RESEND 17/17] MIPS: lantiq: enable oprofile support on lantiq targets John Crispin
2012-01-13 12:38 ` [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code Ralf Baechle
16 siblings, 2 replies; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin, Felix Fietkau
The patch makes the oprofile code use the performance counters irq.
This patch is written by Felix Fietkau.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/kernel/cevt-r4k.c | 2 +-
arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++
2 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd9..bc702c8 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -84,7 +84,7 @@ out:
struct irqaction c0_compare_irqaction = {
.handler = c0_compare_interrupt,
- .flags = IRQF_PERCPU | IRQF_TIMER,
+ .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
.name = "timer",
};
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1..86cf234 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -298,6 +298,11 @@ static void reset_counters(void *arg)
}
}
+static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
+{
+ return mipsxx_perfcount_handler();
+}
+
static int __init mipsxx_init(void)
{
int counters;
@@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
save_perf_irq = perf_irq;
perf_irq = mipsxx_perfcount_handler;
+ if (cp0_perfcount_irq >= 0)
+ return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
+ IRQF_SHARED, "Perfcounter", save_perf_irq);
+
return 0;
}
@@ -381,6 +390,9 @@ static void mipsxx_exit(void)
{
int counters = op_model_mipsxx_ops.num_counters;
+ if (cp0_perfcount_irq >= 0)
+ free_irq(cp0_perfcount_irq, save_perf_irq);
+
counters = counters_per_cpu_to_total(counters);
on_each_cpu(reset_counters, (void *)(long)counters, 1);
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set
2012-01-11 20:44 ` [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
@ 2012-01-12 11:37 ` Sergei Shtylyov
2012-01-12 15:38 ` Sergei Shtylyov
1 sibling, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2012-01-12 11:37 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, linux-mips, Felix Fietkau
Hello.
On 12-01-2012 0:44, John Crispin wrote:
> The patch makes the oprofile code use the performance counters irq.
> This patch is written by Felix Fietkau.
Perhaps you should have marked it as "From: Felix Fietkau
<nbd@openwrt.org>" in the first line of the mail?
> Signed-off-by: Felix Fietkau <nbd@openwrt.org>
> Signed-off-by: John Crispin <blogic@openwrt.org>
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set
2012-01-11 20:44 ` [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
2012-01-12 11:37 ` Sergei Shtylyov
@ 2012-01-12 15:38 ` Sergei Shtylyov
2012-01-12 14:49 ` Guenter Roeck
2012-01-12 17:02 ` Ralf Baechle
1 sibling, 2 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2012-01-12 15:38 UTC (permalink / raw)
To: John Crispin; +Cc: Ralf Baechle, linux-mips, Felix Fietkau
Hello.
On 01/11/2012 11:44 PM, John Crispin wrote:
> The patch makes the oprofile code use the performance counters irq.
> This patch is written by Felix Fietkau.
> Signed-off-by: Felix Fietkau<nbd@openwrt.org>
> Signed-off-by: John Crispin<blogic@openwrt.org>
> @@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
> save_perf_irq = perf_irq;
> perf_irq = mipsxx_perfcount_handler;
>
> + if (cp0_perfcount_irq>= 0)
BTW, I just noticed. IRQ0 is not a valid IRQ in Linux, request_irq() should
fail when passed 0, so this and following check should be '> 0'.
> + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
> + IRQF_SHARED, "Perfcounter", save_perf_irq);
> +
> return 0;
> }
>
> @@ -381,6 +390,9 @@ static void mipsxx_exit(void)
> {
> int counters = op_model_mipsxx_ops.num_counters;
>
> + if (cp0_perfcount_irq>= 0)
> + free_irq(cp0_perfcount_irq, save_perf_irq);
> +
> counters = counters_per_cpu_to_total(counters);
> on_each_cpu(reset_counters, (void *)(long)counters, 1);
>
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set
2012-01-12 15:38 ` Sergei Shtylyov
@ 2012-01-12 14:49 ` Guenter Roeck
2012-01-12 17:02 ` Ralf Baechle
1 sibling, 0 replies; 33+ messages in thread
From: Guenter Roeck @ 2012-01-12 14:49 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: John Crispin, Ralf Baechle, linux-mips@linux-mips.org,
Felix Fietkau
On Thu, Jan 12, 2012 at 10:38:22AM -0500, Sergei Shtylyov wrote:
> Hello.
>
> On 01/11/2012 11:44 PM, John Crispin wrote:
>
> > The patch makes the oprofile code use the performance counters irq.
>
> > This patch is written by Felix Fietkau.
>
> > Signed-off-by: Felix Fietkau<nbd@openwrt.org>
> > Signed-off-by: John Crispin<blogic@openwrt.org>
>
> > @@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
> > save_perf_irq = perf_irq;
> > perf_irq = mipsxx_perfcount_handler;
> >
> > + if (cp0_perfcount_irq>= 0)
>
> BTW, I just noticed. IRQ0 is not a valid IRQ in Linux, request_irq() should
> fail when passed 0, so this and following check should be '> 0'.
>
There is also the little matter of coding style. Watch out for chapter 3.
Guenter
> > + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
> > + IRQF_SHARED, "Perfcounter", save_perf_irq);
> > +
> > return 0;
> > }
> >
> > @@ -381,6 +390,9 @@ static void mipsxx_exit(void)
> > {
> > int counters = op_model_mipsxx_ops.num_counters;
> >
> > + if (cp0_perfcount_irq>= 0)
> > + free_irq(cp0_perfcount_irq, save_perf_irq);
> > +
> > counters = counters_per_cpu_to_total(counters);
> > on_each_cpu(reset_counters, (void *)(long)counters, 1);
> >
>
> WBR, Sergei
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set
2012-01-12 15:38 ` Sergei Shtylyov
2012-01-12 14:49 ` Guenter Roeck
@ 2012-01-12 17:02 ` Ralf Baechle
1 sibling, 0 replies; 33+ messages in thread
From: Ralf Baechle @ 2012-01-12 17:02 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: John Crispin, linux-mips, Felix Fietkau
On Thu, Jan 12, 2012 at 06:38:22PM +0300, Sergei Shtylyov wrote:
> >@@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
> > save_perf_irq = perf_irq;
> > perf_irq = mipsxx_perfcount_handler;
> >
> >+ if (cp0_perfcount_irq>= 0)
>
> BTW, I just noticed. IRQ0 is not a valid IRQ in Linux,
> request_irq() should fail when passed 0, so this and following check
> should be '> 0'.
In a normal configuration that is in a discrete processor or in a MIPS
core where the performance IRQ is just routed back into the core the
lowest sensible value for cp0_perfcount_irq is 2, so there is no
immediate problem there.
IRQ 0 is ok for static use; dynamic use is problematic. This case is
even more problematic because the interrupt might be shared with the
timer and the timer interrupt is allocated statically (see cevt-r4k.c)
but the performance counter interrupt later allocated dynamically with
IRQF_SHARED.
Ralf
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH RESEND 17/17] MIPS: lantiq: enable oprofile support on lantiq targets
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (14 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 16/17] MIPS: make oprofile use cp0_perfcount_irq if it is set John Crispin
@ 2012-01-11 20:44 ` John Crispin
2012-01-17 14:22 ` Ralf Baechle
2012-01-13 12:38 ` [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code Ralf Baechle
16 siblings, 1 reply; 33+ messages in thread
From: John Crispin @ 2012-01-11 20:44 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips, John Crispin
This patch sets the performance counters irq for Lantiq SoCs.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/lantiq/irq.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 3b8cea5..6304a80 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -40,6 +40,9 @@
#define MAX_EIU 6
+/* the performance counter */
+#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
+
/* irqs generated by device attached to the EBU need to be acked in
* a special manner
*/
@@ -317,6 +320,8 @@ void __init arch_init_irq(void)
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif
+
+ cp0_perfcount_irq = LTQ_PERF_IRQ;
}
unsigned int __cpuinit get_c0_compare_int(void)
--
1.7.7.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code
2012-01-11 20:44 [PATCH RESEND 01/17] MIPS: lantiq: reorganize xway code John Crispin
` (15 preceding siblings ...)
2012-01-11 20:44 ` [PATCH RESEND 17/17] MIPS: lantiq: enable oprofile support on lantiq targets John Crispin
@ 2012-01-13 12:38 ` Ralf Baechle
16 siblings, 0 replies; 33+ messages in thread
From: Ralf Baechle @ 2012-01-13 12:38 UTC (permalink / raw)
To: John Crispin; +Cc: linux-mips
On Wed, Jan 11, 2012 at 09:44:18PM +0100, John Crispin wrote:
> +static inline void ltq_ebu_w32_mask(u32 c, u32 s, u32 r) {
> + ltq_ebu_w32((ltq_ebu_r32(r) & ~c) | s, r);
> +}
> +
> +/* cgu access */
> +static inline void ltq_cgu_w32(u32 v, u32 r) {
> + ltq_w32(v, ltq_cgu_membase + r);
> +};
> +static inline u32 ltq_cgu_r32(u32 r) {
> + return ltq_r32(ltq_cgu_membase + r);
> +};
> +static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r) {
> + ltq_cgu_w32((ltq_cgu_r32(r) & ~c) | s, r);
> +}
Documentation/CodingStyle:
[...]
However, there is one special case, namely functions: they have the
opening brace at the beginning of the next line, thus:
int function(int x)
{
body of function
}
Heretic people all over the world have claimed that this inconsistency
is ... well ... inconsistent, but all right-thinking people know that
(a) K&R are _right_ and (b) K&R are right. Besides, functions are
special anyway (you can't nest them in C).
[...]
So this formatting is heretic. Pray 10 CodingStyle to Saint K&R.
Ralf
^ permalink raw reply [flat|nested] 33+ messages in thread