Re: DSS2/PM on 3.2 broken?

[NeilBrown <neilb@suse.de>]

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On Wed, 18 Jan 2012 13:42:20 +0200 Tomi Valkeinen <tomi.valkeinen@ti.com>
wrote:

> On Wed, 2012-01-18 at 22:15 +1100, NeilBrown wrote:
> > On Wed, 18 Jan 2012 09:13:59 +0200 Tomi Valkeinen <tomi.valkeinen@ti.com>
> > wrote:
> > 
> > > On Fri, 2012-01-13 at 22:20 +1100, NeilBrown wrote:
> > > > Having CPUIDLE makes the DSS2 problem worse: lots of 
> > > > 
> > > > [   21.085113] omapdss DISPC error: SYNC_LOST on channel lcd,
> > > > restarting the output with video overlays disabled
> > > > 
> > > > messages whenever the CPU isn't busy.
> > > 
> > > I'm not sure if it is the case here, but DSS has restrictions about the
> > > max DSS clocks on different OPPs. For example, on OMAP4430 LCD clock
> > > maximum is 186MHz at OPP100, and 93MHz at OPP50. So it's a quite big
> > > drop, causing problems with all but the rather small displays.
> > > 
> > > And the DSS driver doesn't have any support to handle this at the
> > > moment, as there isn't support in the PM framework to do this. I think
> > > the only way to handle this at the moment is for the DSS driver to set
> > > an arbitrarily high constraint on, say, mem throughput, and hope that it
> > > keeps the OMAP in the required OPP.
> > > 
> > >  Tomi
> > > 
> > 
> > This LCD panel on this device sets:
> >    .pixel_clock	= 22000,
> > in the "struct omap_video_timings" so I'm guessing that is 22MHz?
> 
> No, that's the pixel clock. There are probably limitations on the pix
> clock also, but usually the problem is the functional clocks, which need
> to be n x pck, where n depends on the needs for scaling.

Ahh..

   cat /sys/kernel/debug/omapdss/clk

is below and reports 66461538 for fck, so 66MHz?  Still safe for OPP50.

And disabling SMART REFLEX had no obvious effect.

If you can think of anything else I could try to explore to narrow down 
the source of this, I am very happy to test or examine anything you suggest.

Thanks,
NeilBrown



- DSS -
dpll4_ck 864000000
DSS_FCK (DSS1_ALWON_FCLK) = 864000000 / 13  = 66461538
- DISPC -
dispc fclk source = DSS_FCK (DSS1_ALWON_FCLK)
fck		66461538        
- LCD1 -
lcd1_clk source = DSS_FCK (DSS1_ALWON_FCLK)
lck		66461538        lck div	1
pck		22153846        pck div	3
- DSI1 PLL -
dsi pll source = pclkfree
Fint		0               regn 0
CLKIN4DDR	0               regm 0
DSS_FCK (DSS1_ALWON_FCLK)	0               regm_dispc 0	(off)
DSS_FCK (DSS1_ALWON_FCLK)	0               regm_dsi 0	(off)
- DSI1 -
dsi fclk source = DSS_FCK (DSS1_ALWON_FCLK)
DSI_FCLK	66461538
DDR_CLK		0
TxByteClkHS	0
LP_CLK		0



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